Rev. 3.0, 09/98, page 144 of 361
(1) Upper byte write
Bus interface
CPU writes
data H'AA
TEMP
[H'AA]
FRC H
[ ]
FRC L
[ ]
Module data bus
(2) Lower byte write
Bus interface
CPU writes
data H'55
TEMP
[H'AA]
FRC H
[H'AA]
FRC L
[H'55]
Module data bus
Figure 7.3 (a) Write Access to FRC (when CPU writes H'AA55)
