Hardware manual

Rev. 3.0, 09/98, page 141 of 361
7.2.7 Timer Output Compare Control Register (TOCR)H'FF97
Bit:76543210
OCRS OEA OEB OLVLA OLVLB
Initial value:11100000
Read/Write: R/W R/W R/W R/W R/W
The TOCR is an 8-bit readable/writable register that controls the output compare function.
The TOCR is initialized to H'E0 at a reset and in the standby modes.
Bits 7 to 5Reserved: These bits cannot be modified and are always read as “1.”
Bit 4Output Compare Register Select (OCRS): When the CPU accesses addresses H'FF94
and H'FF95, this bit directs the access to either OCRA or OCRB. These two registers share the
same addresses as follows:
Upper byte of OCRA and upper byte of OCRB: H'FF94
Lower byte of OCRA and lower byte of OCRB: H'FF95
Bit 4
OCRS Description
0 The CPU can access OCRA. (Initial value)
1 The CPU can access OCRB.
Bit 3Output Enable A (OEA): This bit enables or disables output of the output compare A
signal (FTOA).
Bit 3
OEA Description
0 Output compare A output is disabled. (Initial value)
1 Output compare A output is enabled.
Bit 2Output Enable B (OEB): This bit enables or disables output of the output compare B
signal (FTOB).
Bit 2
OEB Description
0 Output compare B output is disabled. (Initial value)
1 Output compare B output is enabled.