Hardware manual

Rev. 3.0, 09/98, page 140 of 361
Bit 4Input Edge Select D (IEDGD): This bit causes input capture D events to be recognized
on the selected edge of the input capture D signal (FTID).
Bit 4
IEDGD Description
0 Input capture D events are recognized on the falling edge of FTID. (Initial value)
1 Input capture D events are recognized on the rising edge of FTID.
Bit 3Buffer Enable A (BUFEA): This bit selects whether to use ICRC as a buffer register for
ICRA.
Bit 3
BUFEA Description
0 ICRC is used for input capture C. (Initial value)
1 ICRC is used as a buffer register for input capture A. Input C is not captured.
Bit 2Buffer Enable B (BUFEB): This bit selects whether to use ICRD as a buffer register for
ICRB.
Bit 2
BUFEB Description
0 ICRD is used for input capture D. (Initial value)
1 ICRD is used as a buffer register for input capture B. Input D is not captured.
Bits 1 and 0Clock Select (CKS1 and CKS0): These bits select external clock input or one of
three internal clock sources for the FRC. External clock pulses are counted on the rising edge.
Bit 1
CKS1
Bit 0
CKS0 Description
00φ/2 Internal clock source (Initial value)
01φ/8 Internal clock source
10φ/32 Internal clock source
1 1 External clock source (rising edge)