Hardware manual
Rev. 3.0, 09/98, page 139 of 361
7.2.6 Timer Control Register (TCR)-H'FF96
Bit:76543210
IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0
Initial value:00000000
Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W
The TCR is an 8-bit readable/writable register that selects the rising or falling edge of the input
capture signals, enables the input capture buffer mode, and selects the FRC clock source.
The TCR is initialized to H'00 at a reset and in the standby modes.
Bit 7Input Edge Select A (IEDGA): This bit causes input capture A events to be recognized
on the selected edge of the input capture A signal (FTIA).
Bit 7
IEDGA Description
0 Input capture A events are recognized on the falling edge of FTIA. (Initial value)
1 Input capture A events are recognized on the rising edge of FTIA.
Bit 6Input Edge Select B (IEDGB): This bit causes input capture B events to be recognized
on the selected edge of the input capture B signal (FTIB).
Bit 6
IEDGB Description
0 Input capture B events are recognized on the falling edge of FTIB. (Initial value)
1 Input capture B events are recognized on the rising edge of FTIB.
Bit 5Input Edge Select C (IEDGC): This bit causes input capture C events to be recognized
on the selected edge of the input capture C signal (FTIC).
Bit 5
IEDGC Description
0 Input capture C events are recognized on the falling edge of FTIC. (Initial value)
1 Input capture C events are recognized on the rising edge of FTIC.