Hardware manual
Rev. 3.0, 09/98, page 136 of 361
7.2.5 Timer Control/Status Register (TCSR)H'FF91
Bit:76543210
ICFA ICFB ICFC ICFD OCFA OCFB OVF CCLRA
Initial value:00000000
Read/Write: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/W
The TCSR is an 8-bit readable and partially writable* register that contains the seven interrupt
flags and specifies whether to clear the counter on compare-match A (when the FRC and OCRA
values match).
Note: Software can write a “0” in bits 7 to 1 to clear the flags, but cannot write a “1” in these
bits.
The TCSR is initialized to H'00 at a reset and in the standby modes.
Bit 7Input Capture Flag A (ICFA):
This status bit is set to “1” to flag an input capture A
event. If BUFEA = “0,” ICFA indicates that the FRC value has been copied to ICRA. If BUFEA
= “1,” ICFA indicates that the old ICRA value has been moved into ICRC and the new FRC value
has been copied to ICRA.
ICFA must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 7
ICFA Description
0 To clear ICFA, the CPU must read ICFA after it has been set to “1,” (Initial value)
then write a “0” in this bit.
1 This bit is set to 1 when an FTIA input signal causes the FRC value
to be copied to ICRA.