Hardware manual

Rev. 3.0, 09/98, page 135 of 361
Bit 4Input Capture Interrupt D Enable (ICIDE): This bit selects whether to request input
capture interrupt D (ICID) when input capture flag D (ICFD) in the timer status/control register
(TCSR) is set to “1.”
Bit 4
ICIDE Description
0 Input capture interrupt request D (ICID) is disabled. (Initial value)
1 Input capture interrupt request D (ICID) is enabled.
Bit 3Output Compare Interrupt A Enable (OCIAE): This bit selects whether to request
output compare interrupt A (OCIA) when output compare flag A (OCFA) in the timer
status/control register (TCSR) is set to “1.”
Bit 3
OCIAE Description
0 Output compare interrupt request A (OCIA) is disabled. (Initial value)
1 Output compare interrupt request A (OCIA) is enabled.
Bit 2Output Compare Interrupt B Enable (OCIBE): This bit selects whether to request
output compare interrupt B (OCIB) when output compare flag B (OCFB) in the timer
status/control register (TCSR) is set to “1.”
Bit 2
OCIBE Description
0 Output compare interrupt request B (OCIB) is disabled. (Initial value)
1 Output compare interrupt request B (OCIB) is enabled.
Bit 1Timer overflow Interrupt Enable (OVIE): This bit selects whether to request a free-
running timer overflow interrupt (FOVI) when the timer overflow flag (OVF) in the timer
status/control register (TCSR) is set to “1.”
Bit 1
OVIE Description
0 Timer overflow interrupt request (FOVI) is disabled. (Initial value)
1 Timer overflow interrupt request (FOVI) is enabled.
Bit 0Reserved: This bit cannot be modified and is always read as “1.”