Hardware manual

Rev. 3.0, 09/98, page 134 of 361
7.2.4 Timer Interrupt Enable Register (TIER)-H'FF90
Bit:76543210
ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE 
Initial value:00000001
Read/Write: R/W R/W R/W R/W R/W R/W R/W 
The TIER is an 8-bit readable/writable register that enables and disables interrupts.
The TIER is initialized to H'01 (all interrupts disabled) at a reset and in the standby modes.
Bit 7Input Capture Interrupt A Enable (ICIAE): This bit selects whether to request input
capture interrupt A (ICIA) when input capture flag A (ICFA) in the timer status/control register
(TCSR) is set to “1.”
Bit 7
ICIAE Description
0 Input capture interrupt request A (ICIA) is disabled. (Initial value)
1 Input capture interrupt request A (ICIA) is enabled.
Bit 6Input Capture Interrupt B Enable (ICIBE): This bit selects whether to request input
capture interrupt B (ICIB) when input capture flag B (ICFB) in the timer status/control register
(TCSR) is set to “1.”
Bit 6
ICIBE Description
0 Input capture interrupt request B (ICIB) is disabled. (Initial value)
1 Input capture interrupt request B (ICIB) is enabled.
Bit 5Input Capture Interrupt C Enable (ICICE): This bit selects whether to request input
capture interrupt C (ICIC) when input capture flag C (ICFC) in the timer status/control register
(TCSR) is set to “1.”
Bit 5
ICICE Description
0 Input capture interrupt request C (ICIC) is disabled. (Initial value)
1 Input capture interrupt request C (ICIC) is enabled.