Hardware manual

Rev. 3.0, 09/98, page 133 of 361

Table 7.3 Buffered Input Capture Edge Selection (Example)

IEDGA IEDGC Input Capture Edge

0 0 Captured on falling edge of input capture A (FTIA) (Initial value)

0 1 Captured on both rising and falling edges of input capture A (FTIA)

1 1 Captured on rising edge of input capture A (FTIA)

Because the input capture registers are 16-bit registers, a temporary register (TEMP) is used when

they are read. See section 7.3, “CPU Interface,” for details.

To ensure input capture, the width of the input capture pulse (FTIA, FTIB, FTIC, FTID) should be

at least 1.5 system clock periods (1.5⋅φ). When triggering is enabled on both edges, the input

capture pulse width should be at least 2.5 system clock periods.

The input capture registers are initialized to H'0000 at a reset and in the standby modes.

Note: When input capture is detected, the FRC value is transferred to the input capture register

even if the input capture flag is already set.