Hardware manual

Rev. 3.0, 09/98, page 132 of 361
Input capture can be buffered by using the input capture registers in pairs. When the BUFEA bit
in the timer control register (TCR) is set to “1,” ICRC is used as a buffer register for ICRA as
shown in figure 7.2. When an FTIA input is received, the old ICRA contents are moved into
ICRC, and the new FRC count is copied into ICRA.
FTIA
BUFEA
IEDGA IEDGC
ICRC
ICRA FRC
Edge detect and
capture signal
generating circuit
BUFEA
IEDGA
IEDGC
ICRC
ICRA
FRC
: Buffer Enable A
: Edge Select A
: Input Edge Select C
: Input Capture Register C
: Input Capture Register A
: Free-Running Counter
Figure 7.2 Input Capture Buffering
Similarly, when the BUFEB bit in TIER is set to “1,” ICRD is used as a buffer register for ICRB.
When input capture is buffered, if the two input edge bits are set to different values (IEDGA ≠
IEDGC or IEDGB ≠ IEDGD), then input capture is triggered on both the rising and falling edges
of the FTIA or FTIB input signal. If the two input edge bits are set to the same value (IEDGA =
IEDGC or IEDGB = IEDGD), then input capture is triggered on only one edge.