Hardware manual

Rev. 3.0, 09/98, page 130 of 361
Table 7.2 Register Configuration (cont)
Name Abbreviation R/W Initial Value Address
Input capture register B (High) ICRB (H) R H'00 H'FF9A
Input capture register B (Low) ICRB (L) R H'00 H'FF9B
Input capture register C (High) ICRC (H) R H'00 H'FF9C
Input capture register C (Low) ICRC (L) R H'00 H'FF9D
Input capture register D (High) ICRD (H) R H'00 H'FF9E
Input capture register D (Low) ICRD (L) R H'00 H'FF9F
7.2 Register Descriptions
7.2.1 Free-Running Counter (FRC)H'FF92
Bit:1514131211109876543210
Initial value:0000000000000000
Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The FRC is a 16-bit readable/writable up-counter that increments on an internal pulse generated
from a clock source. The clock source is selected by the clock select 1 and 0 bits (CKS1 and
CKS0) of the timer control register (TCR).
When the FRC overflows from H'FFFF to H'0000, the overflow flag (OVF) in the timer
control/status register (TCSR) is set to “1.”
Because the FRC is a 16-bit register, a temporary register (TEMP) is used when the FRC is
written or read. See section 7.3, “CPU Interface,” for details.
The FRC is initialized to H'0000 at a reset and in the standby modes. It can also be cleared by
compare-match A.