Hardware manual

Rev. 3.0, 09/98, page 120 of 361
Port 9 Data Direction Register (P9DDR)H'FFC0
Bit 76543210
P9
7
DDR P9
6
DDR P9
5
DDR P9
4
DDR P9
3
DDR P9
2
DDR P9
1
DDR P9
0
DDR
Modes 1 and 2
Initial value 01000000
Read/Write W  WWWWWW
Mode 3
Initial value 00000000
Read/Write W W W W W W W W
P9DDR is an 8-bit register that selects the direction of each pin in port 9. A pin functions as an
output pin if the corresponding bit in P9DDR is set to “1,” and as in input pin if the bit is cleared
to “0.”
Port 9 Data Register (P9DR)H'FFC1
Bit:76543210
P9
7
P9
6
P9
5
P9
4
P9
3
P9
2
P9
1
P9
0
Initial value: 0
*
000000
Read/Write: R/W R R/W R/W R/W R/W R/W R/W
Note: Determined by the level at pin P9
6
.
P9DR is an 8-bit register containing the data for pins P9
7
to P9
0
. When the CPU reads P9DR, for
output pins (P9DDR = “1”) it reads the value in the P9DR latch, but for input pins (P9DDR =
“0”), it obtains the logic level directly from the pin, bypassing the P9DR latch. This also applies
to pins used for interrupt input, A/D trigger input, clock output, and control signal input or output.
Pins P9
0
, P9
1
, and P9
2
: Can be used for general-purpose input or output, interrupt request input,
or A/D trigger input. See table 6.21. If a pin is used for interrupt or A/D trigger input, its data
direction bit should be cleared to “0,” so that the output from P9DR will not generate an interrupt
request or A/D trigger signal.
Pins P9
3
, P9
4
, and P9
5
: In modes 1 and 2 (the expanded modes), these pins are used for output of
the RD, WR, and AS bus control signals. They are unaffected by the values in P9DDR and P9DR.
In mode 3 (single-chip mode), these pins can be used for general-purpose input or output.
Pin P9
6
: In modes 1 and 2, this pin is used for system clock (φ) output.
In mode 3, this pin is used for general-purpose input if P96DDR is cleared to “0,” or system clock
output if P9
6
DDR is set to “1.”