Hardware manual

Rev. 3.0, 09/98, page 2 of 361
Table 1.1 Features
Item Specification
CPU Two-way general register configuration
• Eight 16-bit registers, or
• Sixteen 8-bit registers
High-speed operation
• Maximum clock rate: 10MHz
• Add/subtract: 0.2µs
• Multiply/divide: 1.4µs
Streamlined, concise instruction set
• Instruction length: 2 or 4 bytes
• Register-register arithmetic and logic operations
• MOV instruction for data transfer between registers and memory
Instruction set features
• Multiply instruction (8 bits × 8 bits)
• Divide instruction (16 bits ÷ 8 bits)
• Bit-accumulator instructions
• Register-indirect specification of bit positions
Memory
• H8/338: 48k-byte ROM; 2k-byte RAM
• H8/337: 32k-byte ROM; 1k-byte RAM
• H8/336: 24k-byte ROM; 1k-byte RAM
16-bit free-
running timer
(1 channel)
• One 16-bit free-running counter (can also count external events)
• Two output-compare lines
• Four input capture lines (can be buffered)
8-bit timer
(2 channels)
Each channel has
• One 8-bit up-counter (can also count external events)
• Two time constant registers
PWM timer
(2 channels)
• Duty cycle can be set from 0 to 100%
• Resolution: 1/250
Serial
communication
interface (SCI)
(2 channels)
• Asynchronous or clocked synchronous mode (selectable)
• Full duplex: can transmit and receive simultaneously
• On-chip baud rate generator