Hardware manual

Rev. 3.0, 09/98, page 114 of 361
Port 8 Data Register (P8DR)H'FFBF
Bit:76543210
P8
6
P8
5
P8
4
P8
3
P8
2
P8
1
P8
0
Initial value:10000000
Read/Write:  R/W R/W R/W R/W R/W R/W R/W
P8DR is an 8-bit register containing the data for pins P8
6
to P8
0
. When the CPU reads P8DR, for
output pins (P8DDR = “1”) it reads the value in the P8DR latch, but for input pins (P8DDR =
“0”), it obtains the logic level directly from the pin, bypassing the P8DR latch. This also applies
to pins used for interrupt input and serial communication.
Bit 7 is reserved. It cannot be modified, and is always read as “1.”
Pins 8
0
to P8
3
: These pins are available for general-purpose input or output.
Pin P8
4
: This pin has the same functions in all modes. It can be used for general-purpose input or
output, for output of serial transmit data (TxD
1
), or for IRQ
3
input. When used for TxD
1
output,
this pin is unaffected by the values in P8DDR and P8DR. When this pin is used for IRQ
3
input,
P8
4
DDR should normally be cleared to “0,” so that the value in P8DR will not generate interrupts.
Pin P8
5
: This pin has the same functions in all modes. It can be used for general-purpose input or
output, for input of serial receive data (RxD
1
), or for IRQ
4
input. When used for RxD
1
input, this
pin is unaffected by the values in P8DDR and P8DR. When this pin is used for IRQ
4
input,
P8
5
DDR should normally be cleared to “0,” so that the value in P8DR will not generate interrupts.
Pin P8
6
: This pin has the same functions in all modes. It can be used for general-purpose input or
output, for serial clock input or output (SCK
1
), or for IRQ
5
input. When this pin is used for IRQ
5
input, P8
6
DDR should normally be cleared to “0,” so that the value in P8DR will not generate
interrupts.
When used for SCK
1
input or output, this pin is unaffected by the values in P8DDR and P8DR.
Reset: A reset clears bits P8
6
DDR to P8
0
DDR to “0” and clears the serial control bits and
interrupt enable bits to “0,” making P8
6
to P8
0
into input port pins.
Hardware Standby Mode: All pins are placed in the high-impedance state.
Software Standby Mode: In the software standby mode, the serial control register is initialized,
but the interrupt enable register, P8DDR, and P8DR remain in their previous states. Pins that were
being used for serial communication revert to general-purpose input or output, depending on the
value in P8DDR. Other pins remain in their previous state. Output pins output the values in
P8DR.