Hardware manual

Rev. 3.0, 09/98, page 107 of 361
Figures 6.6 (a) to 6.6 (d) shows schematic diagrams of port 6.
P6n
RP6
Reset
Internal data bus
Reset
WP6
WP6D
R
R
Q
Q
D
D
P6n DR
P6n DDR
C
C
WP6D:
WP6:
RP6:
n = 0, 2 - 5
Write Port 6 DDR
Write Port 6
Read Port 6
Free-running
timer module
Input capture
input, counter
clock input
Figure 6.6 (a) Port 6 Schematic Diagram (Pins P6
0
, P6
2
, P6
3
, P6
4
, and P6
5
)