Rev. 3.0, 09/98, page 104 of 361
RP5
Reset
Reset
WP5
WP5D
R
R
Q
Q
D
D
P52 DR
P52 DDR
C
C
WP5D:
WP5:
RP5:
Write Port 5 DDR
Write Port 5
Read Port 5
SCI module
Internal data bus
Clock input enable
Clock output enable
Clock output
Clock input
P52
Figure 6.5 (c) Port 5 Schematic Diagram (Pin P5
2
)
