Hardware manual

Rev. 3.0, 09/98, page 101 of 361
Port 5 Data Register (P5DR)H'FFBA
Bit:76543210
P5
2
P5
1
P5
0
Initial value:11111000
Read/Write: R/W R/W R/W
P5DR is an 8-bit register containing the data for pins P5
2
to P5
0
. When the CPU reads P5DR, for
output pins (P5DDR = “1”) it reads the value in the P5DR latch, but for input pins (P5DDR =
“0”), it obtains the logic level directly from the pin, bypassing the P5DR latch. This also applies
to pins used for serial communication.
Pin P5
0
: This pin can be used for general-purpose input or output, or for output of serial transmit
data (TxD
0
). When used for TxD
0
output, this pin is unaffected by the values in P5DDR and
P5DR.
Pin P5
1
: This pin can be used for general-purpose input or output, or for input of serial receive
data (RxD
0
). When used for RxD
0
input, this pin is unaffected by P5DDR and P5DR.
Pin P5
2
: This pin can be used for general-purpose input or output, or for serial clock input or
output (SCK
0
). When used for SCK
0
input or output, this pin is unaffected by P5DDR and P5DR.
Reset and Hardware Standby Mode: A reset or entry to the hardware standby mode makes all
pins of port 5 into input port pins.
Software Standby Mode: In the software standby mode, the serial control register is initialized
but P5DDR and P5DR remain in their previous states. All pins become input or output port pins
depending on the setting of P5DDR. Output pins output the values in P5DR.