Hardware manual

Rev. 3.0, 09/98, page 98 of 361
Figures 6.4 (a) and 6.4 (b) show schematic diagrams of port 4.
P4n
RP4
Reset
Internal data bus
Reset
WP4
WP4D
R
R
Q
Q
D
D
P4n DR
P4n DDR
C
C
WP4D:
WP4:
RP4:
n = 0, 2, 3, 5
Write Port 4 DDR
Write Port 4
Read Port 4
8-bit timer module
Counter reset input
Counter clock input
Figure 6.4 (a) Port 4 Schematic Diagram (Pins P4
0
, P4
2
, P4
3
, and P4
5
)