Hardware manual

Rev. 3.0, 09/98, page 97 of 361
Port 4 Data Register (P4DR)H'FFB7
Bit:76543210
P4
7
P4
6
P4
5
P4
4
P4
3
P4
2
P4
1
P4
0
Initial value:00000000
Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W
P4DR is an 8-bit register containing the data for pins P4
7
to P4
0
. When the CPU reads P4DR, for
output pins (P4DDR = “1”) it reads the value in the P4DR latch, but for input pins (P4DDR =
“0”), it obtains the logic level directly from the pin, bypassing the P4DR latch. This also applies
to pins used for timer input or output.
Pins P4
0
, P4
2
, P4
3
, and P4
5
: As indicated in table 6.11, these pins can be used for general-purpose
input or output, or input of 8-bit timer clock and reset signals. When a pin is used for timer signal
input, its P4DDR bit should normally be cleared to “0;” otherwise the timer will receive the value
in P4DR.
Pins P4
1
, P4
4
, P4
6
, and P4
7
: As indicated in table 6.11, these pins can be used for general-purpose
input or output, or for 8-bit timer output (P4
1
and P4
4
) or PWM timer output (P4
6
and P4
7
). Pins
used for timer output are unaffected by the values in P4DDR and P4DR.
Reset and Hardware Standby Mode: A reset or entry to the hardware standby mode clears
P4DDR and P4DR to all “0” and makes all pins into input port pins.
Software Standby Mode: In the software standby mode, the control registers of the 8-bit and
PWM timers are initialized but P4DDR and P4DR remain in their previous states. All pins
become input or output port pins depending on the setting of P4DDR. Output pins output the
values in P4DR.