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Summary of content (369 pages)

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To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd.
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Hitachi Single-Chip Microcomputer H8/338 Series H8/338 HD6473388, HD6433388, HD6413388 H8/337 HD6473378, HD6433378, HD6413378 H8/336 HD6433368 Hardware Manual ADE-602-039B Rev. 3.
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Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice.
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Preface The H8/338 Series is a series of high-performance single-chip microcomputers having a fast H8/300 CPU core and a set of on-chip supporting functions optimized for embedded control. These include ROM, RAM, three types of timers, a serial communication interface, an A/D converter, a D/A converter, I/O ports, and other functions needed in control system configurations, so that compact, high-performance systems can be realized easily.
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Contents Section 1 1.1 1.2 1.3 Overview ........................................................................................................... Overview ........................................................................................................................... Block Diagram .................................................................................................................. Pin Assignments and Functions........................................................................
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3.2 3.3 3.4 System Control Register (SYSCR)H'FFC4 ................................................................... 54 Mode Control Register (MDCR)H'FFC5 ...................................................................... 56 Address Space Map ........................................................................................................... 57 Section 4 4.1 4.2 4.3 4.4 Exception Handling........................................................................................ Overview ....
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.2 7.3 7.4 7.5 7.6 7.7 7.1.3 Input and Output Pins........................................................................................... 129 7.1.4 Register Configuration ......................................................................................... 129 Register Descriptions ........................................................................................................ 130 7.2.1 Free-Running Counter (FRC)H'FF92...............................................................
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Section 9 9.1 9.2 9.3 9.4 PWM Timers.................................................................................................... 179 Overview ........................................................................................................................... 179 9.1.1 Features ................................................................................................................ 179 9.1.2 Block Diagram .............................................................................
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11.2 Register Descriptions ........................................................................................................ 230 11.2.1 A/D Data Registers (ADDR)H'FFE0 to H'FFE6.............................................. 230 11.2.2 A/D Control/Status Register (ADCSR)H'FFE8 ............................................... 230 11.2.3 A/D Control Register (ADCR)H'FFEA............................................................ 233 11.3 Operation......................................................
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Section 15 Power-Down State.......................................................................................... 265 15.1 Overview ........................................................................................................................... 265 15.2 System Control Register: Power-Down Control Bits ........................................................ 266 15.3 Sleep Mode......................................................................................................................
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Appendix C Pin States ....................................................................................................... 356 C.1 Pin States in Each Mode.................................................................................................... 356 Appendix D Timing of Transition to and Recovery from Hardware Standby Mode........................................................................... 358 Appendix E Package Dimensions ................................................................
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Section 1 Overview 1.1 Overview The H8/338 Series of single-chip microcomputers features an H8/300 CPU core and a complement of on-chip supporting modules implementing a variety of system functions. The H8/300 CPU is a high-speed processor with an architecture featuring powerful bitmanipulation instructions, ideally suited for realtime control applications. The on-chip supporting modules implement peripheral functions needed in system configurations.
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Table 1.1 Features Item Specification CPU Two-way general register configuration • Eight 16-bit registers, or • Sixteen 8-bit registers High-speed operation • Maximum clock rate: 10MHz • Add/subtract: 0.2µs • Multiply/divide: 1.
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Table 1.
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1.2 Block Diagram *1 RES STBY NMI MD1 MD0 VCC VCC VSS VSS VSS VSS VSS VSS VSS Clock pulse generator Port 9 Data (High) Port 1 PROM *2 (or masked ROM) P90/ADTRG /IRQ2 P91/IRQ1 P92/IRQ0 P93/RD P94/WR P95/AS P96/Ø P97/WAIT Port 3 P20 /A8 P21 /A9 P2 2 /A10 P2 3 /A11 P2 4 /A12 P2 5 /A13 P2 6 /A14 P2 7 /A15 Data bus (Low) Port 2 P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 CPU H8/300 Address bus XTAL EXTAL Figure 1.1 shows a block diagram of the H8/338 Series.
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1.3 Pin Assignments and Functions 1.3.1 Pin Arrangement 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 P13 /A3 6 P12 /A2 7 P11 /A1 8 P10 /A0 P36 /D6 P30 /D0 VSS P31 /D1 P37 /D7 P32 /D2 VSS P33 /D3 P80 P34 /D4 P81 P35 /D5 P82 11 10 9 P83 P84 /TxD1/IRQ3 P85 /RxD1/IRQ4 P86 /SCK1/IRQ5 Figure 1.2 shows the pin arrangement of the CG-84 package. Figure 1.3 shows the pin arrangement of the CP-84 package. Figure 1.4 shows the pin arrangement of the FP-80A package.
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P86/SCK1/IRQ5 P85/RxD1/IRQ4 P84/TxD1/IRQ3 P83 P82 P81 P80 VSS P37/D7 VSS P36/D6 P35/D5 P34/D4 P33/D3 P32/D2 P31/D1 P30/D0 P10/A0 P11/A1 P12/A2 P13/A3 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 RES XTAL EXTAL MD1 MD0 NMI STBY VCC P52/SCK0 P51/RxD0 P50/TxD0 VSS VSS P97/WAIT P96/Ø P95/AS P94/WR P93/RD P92/IRQ0 P91/IRQ1 P90/IRQ2/ADTRG 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VSS AVCC P70/AN0 P71/AN1 P72/AN2 P73/A
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P13/A3 P12/A2 P11/A1 P10/A0 P30/D0 P31/D1 P32/D2 P33/D3 P34/D4 P35/D5 P36/D6 P37/D7 VSS P80 P81 P82 P83 P84/TxD1/IRQ3 P85/RxD1/IRQ4 P86/SCK1/IRQ5 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RES 1 60 P14 /A4 XTAL 2 59 P15 /A5 EXTAL 3 58 P16 /A6 MD1 4 57 P17 /A7 MD0 5 56 VSS NMI 6 55 P20/A8 STBY 7 54 P21/A9 VCC 8 53 P22/A10 P52/SCK0 9 52 P23/A11 P51/RxD0 10 51 P24/A12 P50/TxD0 11 50 P25/A13 VSS 12 49 P26/A14 P97/WAIT 13 48
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1.3.2 Pin Functions (1) Pin Assignments in Each Operating Mode: Table 1.2 lists the assignments of the pins of the FP-80A, CP-84, and CG-84 packages in each operating mode. Table 1.2 Pin Assignments in Each Operating Mode Pin No.
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Table 1.2 Pin Assignments in Each Operating Mode (cont) Pin No.
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Table 1.2 Pin Assignments in Each Operating Mode (cont) Pin No.
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(2) Pin Functions: Table 1.3 gives a concise description of the function of each pin. Table 1.3 Pin Functions Pin No. Type Symbol CG-84 CP-84 FP-80A I/O Name and Function Power VCC 19, 60 8, 47 I Power: Connected to the power supply (+5V). Connect both VCC pins to the system power supply (+5V). VSS 2, 4, 23, 12, 56, 24, 41, 73 64, 70 I Ground: Connected to ground (0V). Connect all VSS pins to the system power supply (0V). XTAL 13 2 I Crystal: Connected to a crystal oscillator.
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Table 1.3 Pin Functions (cont) Pin No. Type CG-84 CP-84 FP-80A I/O Name and Function 25 13 I Wait: Requests the CPU to insert TW states into the bus cycle when an external address is accessed. RD 29 17 O Read: Goes Low to indicate that the CPU is reading an external address. WR 28 16 O Write: Goes Low to indicate that the CPU is writing to an external address. AS 27 15 O Address Strobe: Goes Low to indicate that there is a valid address on the address bus.
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Table 1.3 Pin Functions (cont) Pin No. CG-84 CP-84 FP-80A I/O Name and Function 34 39 22 27 O FRT Output compare A and B: Output pins controlled by comparators A and B of the freerunning timer. FTCI 33 21 I FRT counter Clock Input: Input pin for an external clock signal for the free-running timer. FTIA to FTID 35 to 38 23 to 26 I FRT Input capture A to D: Input capture pins for the free-running timer.
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Table 1.3 Pin Functions (cont) Pin No. Type Symbol CG-84 CP-84 Generalpurpose I/O P17 to P10 71 to 78 57 to 64 I/O Port 1: An 8-bit input/output port with programmable MOS input pull-ups and LED driving capability. The direction of each bit can be selected in the port 1 data direction register (P1DDR). P27 to P20 61 to 63, 48 to 55 I/O 65 to 69 Port 2: An 8-bit input/output port with programmable MOS input pull-ups and LED driving capability.
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Section 2 CPU 2.1 Overview The H8/338 Series has the H8/300 CPU: a fast central processing unit with eight 16-bit general registers (also configurable as 16 eight-bit registers) and a concise instruction set designed for high-speed operation. 2.1.1 Features The main features of the H8/300 CPU are listed below.
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2.2 Register Configuration Figure 2.1 shows the register structure of the CPU. There are two groups of registers: the general registers and control registers. 7 07 0 R0H R0L R1H R1L R2H R2L R3H R3L R4H R4L R5H R5L R6H R6L R7H (SP) 15 R7L SP: Stack Pointer 0 PC: Program Counter PC 7 6 5 4 3 2 1 0 CCR I U H U N Z V C CCR: Condition Code Register Carry flag Overflow flag Zero flag Negative flag Half-carry flag Interrupt mask bit User bit User bit Figure 2.1 CPU Registers Rev. 3.
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2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7). When used as data registers, they can be accessed as 16-bit registers, or the high and low bytes can be accessed separately as 8-bit registers (R0H to R7H and R0L to R7L). R7 also functions as the stack pointer, used implicitly by hardware in processing interrupts and subroutine calls.
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“0” otherwise. Similarly, it is set to “1” when the ADD.W, SUB.W, or CMP.W instruction causes a carry or borrow out of bit 11, and cleared to “0” otherwise. It is used implicitly in the DAA and DAS instructions. Bit 4User Bit (U): This bit can be written and read by software (using the LDC, STC, ANDC, ORC, and XORC instructions). Bit 3Negative Flag (N): This flag indicates the most significant bit (sign bit) of the result of an instruction.
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2.3 Addressing Modes 2.3.1 Addressing Mode The H8/300 CPU supports eight addressing modes. Each instruction uses a subset of these addressing modes. Table 2.1 Addressing Modes No.
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• Register Indirect with Pre-Decrement@−Rn The @−Rn mode is used with MOV instructions that store register contents to memory. It is similar to the register indirect mode, but the 16-bit general register specified in the register field of the instruction is decremented before the operand is accessed. The size of the decrement is 1 or 2 depending on the size of the operand: 1 for MOV.B; 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be even.
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2.3.2 How to Calculate Where the Execution Starts Table 2.2 shows how to calculate the Effective Address (EA: Effective Address) for each addressing mode. In the operation instruction, 1) register direct, as well as 6) immediate (for each instruction, ADD.B, ADDX, SUBX, CMP.B, AND, OR, XOR) are used. In the move instruction, 7) program counter relative and 8) all addressing mode to delete the memory indirect can be used.
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Addressing mode and instruction format 1 Register direct, Rn Effective address calculation Effective address 3 0 regm 8 7 op 2 4 3 regm Operands are contained in registers regm and regn 15 0 16-bit register contents 7 6 op 3 4 3 15 0 15 0 15 0 15 0 0 reg Register indirect with displacement, @(d:16, Rn) 15 0 regn 0 regn Register indirect, @Rn 15 3 7 6 op 4 3 15 0 16-bit register contents 0 reg disp disp 4 15 Register indirect with post-increment, @Rn+ 15 7 6 op
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5 Addressing mode and instruction format Effective address calculation Effective address 15 Absolute address @aa:8 8 7 op 0 0 abs @aa:16 15 15 0 0 op abs 6 Immediate #xx:8 15 8 7 op 0 IMM Operand is 1- or 2-byte immediate data #xx:16 15 0 op IMM Rev. 3.0, 09/98, page 23 of 361 7 15 PC-relative @(d:8, PC) 15 8 7 op 0 PC contents 0 disp Sign extension 15 disp 0 Effective Address Calculation (cont) 15 8 7 H'FF Table 2.2 No.
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Table 2.2 No. Addressing mode and instruction format 8 Memory indirect, @@aa:8 15 Effective address calculation 8 7 op Effective address 0 abs 15 8 7 0 H'00 15 Memory contents (16 bits) Notation reg: General register op: Operation code disp: Displacement IMM: Immediate data abs: Absolute address 0 Effective Address Calculation (cont) Rev. 3.0, 09/98, page 24 of 361 Table 3-2.
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2.4 Data Formats The H8/300 CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data. • Bit manipulation instructions operate on 1-bit data specified as bit n (n = 0, 1, 2, ..., 7) in a byte operand. • All arithmetic and logic instructions except ADDS and SUBS can operate on byte data. • The DAA and DAS instruction perform decimal arithmetic adjustments on byte data in packed BCD form. Each nibble of the byte is treated as a decimal digit. • The MOV.W, ADD.W, SUB.W, CMP.
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2.4.1 Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2.3. Data type Register No.
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2.4.2 Memory Data Formats Figure 2.4 indicates the data formats in memory. Word data stored in memory must always begin at an even address. In word access the least significant bit of the address is regarded as “0.” If an odd address is specified, no address error occurs but the access is performed at the preceding even address. This rule affects MOV.W instructions and branching instructions, and implies that only even addresses should be stored in the vector table.
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2.5 Instruction Set Table 2.3 lists the H8/300 instruction set. Table 2.
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Operation Notation Rd General register (destination) Rs General register (source) Rn General register (EAd) Destination operand (EAs) Source operand SP Stack pointer PC Program counter CCR Condition code register N N (negative) flag of CCR Z Z (zero) flag of CCR V V (overflow) flag of CCR C C (carry) flag of CCR #imm Immediate data #xx:3 3-Bit immediate data #xx:8 8-Bit immediate data #xx:16 16-Bit immediate data disp Displacement + Addition − Subtraction × Multiplicat
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2.5.1 Data Transfer Instructions Table 2.4 describes the data transfer instructions. Figure 2.5 shows their object code formats. Table 2.4 Data Transfer Instructions Instruction Size* Function MOV B/W (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:8 or #xx:16, @−Rn, and @Rn+ addressing modes are available for byte or word data.
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15 8 7 Op 0 rm MOV rn Rm Rn @Rm, or @Rm Op rm rn Rn Op rm rn @(d:16, Rm) Rn disp. Op Op rm rn rn abs. Op rn Op rn #imm. @(d:16, Rm) Rn, or Rn @-Rm @aa:8 Rn, or Rn @aa:8 @aa:16 Rn. or @aa:16 #XX:8 Op rn Rn,or @Rm+ Rn abs. Rn #XX:16 Rn Rn #imm. Op rn MOVFRE, MOVTPE rn PUSH, POP abs. Op Legend Op : Operation field rm, rn : Register field disp. : Displacement abs. : Absolute address IMM : immediate data Figure 2.5 Data Transfer Instruction Codes Rev.
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2.5.2 Arithmetic Operations Table 2.5 describes the arithmetic instructions. See figure 2.6 in section 2.5.4, “Shift Operations” for their object codes. Table 2.5 Arithmetic Instructions Instruction Size* Function ADD SUB B/W Rd ± Rs → Rd, Rd + #imm → Rd Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register.
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2.5.3 Logic Operations Table 2.6 describes the four instructions that perform logic operations. See figure 2.6 in section 2.5.4, “Shift Operations,” for their object codes. Table 2.6 Logic Operation Instructions Instruction Size* Function AND B Rd ∧ Rs → Rd, Rd ∧ #imm → Rd Performs a logical AND operation on a general register and another general register or immediate data.
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15 8 Op 7 0 rn rm ADD, AUB, CMP ADDX, SUBX(Rm), MULXU, DIVXU Op rn ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT Op #imm. rn ADD, ADDX, SUBX, CMP (#XX:8) Op rm Op rn Op rn #imm. AND, OR, XOR(Rm) AND, OR, XOR(#XX:8) rn SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR Legend: Op : Operation field rm, rn : Register field IMM : immediate data Figure 2.6 Arithmetic, Logic, and Shift Instruction Codes Rev. 3.
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2.5.5 Bit Manipulations Table 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code formats. Table 2.8 Bit-Manipulation Instructions Instruction Size* Function BSET B 1 → ( of ) Sets a specified bit in a general register or memory to “1.” The bit is specified by a bit number, given in 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory to “0.
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Table 2.8 Bit-Manipulation Instructions (cont) Instruction Size* Function BIXOR B C ⊕ ¬ [( of )] → C XORs the C flag with the inverse of a specified bit in a general register or memory. The bit number is specified by 3-bit immediate data. BLD B ( of ) → C Copies a specified bit in a general register or memory to the C flag. ¬ ( of ) → C Copies the inverse of a specified bit in a general register or memory to the C flag.
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Before Execution of BCLR Instruction P47 P46 P45 P44 P43 P42 P41 P40 Input/output Input Input Output Output Output Output Output Output Pin state Low High Low Low Low Low Low Low DDR 0 0 1 1 1 1 1 1 DR 1 0 0 0 0 0 0 0 Execution of BCLR Instruction BCLR ;clear bit 0 in data direction register #0, @P4DDR After Execution of BCLR Instruction P47 P46 P45 P44 P43 P42 P41 P40 Input/output Output Output Output Output Output Output Output Input Pin stat
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15 8 Op 7 0 #imm. rn BSET, BCLR, BNOT, BTST Operand: register direct (Rn) Bit No.: immediate (#xx:3) Op rm rn Operand: register direct (Rn) Op rn 0 0 0 0 Operand: register indirect (@Rn) #imm. 0 0 0 0 Bit No.: immediate (#xx:3) Op rn 0 0 0 0 Operand: register indirect (@Rn) Op rm 0 0 0 0 Bit No.: register direct (Rm) Bit No.: register direct (Rm) Op Op abs. Op #imm. Op 0 Operand: absolute (@aa:8) 0 0 0 0 0 0 abs. Op rm 0 Bit No.
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2.5.6 Branching Instructions Table 2.9 describes the branching instructions. Figure 2.8 shows their object code formats. Table 2.9 Branching Instructions Instruction Size BCC  Function Branches if condition cc is true.
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15 8 Op 7 0 disp. CC Op rm 0 BCC 0 0 0 Op JMP(@Rm) JMP(@aa:16) abs. Op abs. JMP(@@aa:8) Op disp. BSR Op rm 0 0 0 0 Op JSR(@Rm) JSR(@aa:16) abs. Op abs. Op Legend: Op : Operation field CC : Condition field rm : Register field disp. : Displacement abs. : Absolute address Figure 2.8 Branching Instruction Codes Rev. 3.
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2.5.7 System Control Instructions Table 2.10 describes the system control instructions. Figure 2.9 shows their object code formats. Table 2.10 System Control Instructions Instruction Size Function RTE  Returns from an exception-handling routine. SLEEP  Causes a transition to the power-down state. LDC B Rs → CCR, #imm → CCR Moves immediate data or general register contents to the condition code register. STC B CCR → Rd Copies the condition code register to a specified general register.
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15 8 7 0 Op RTE, SLEEP, NOP Op rn Op #imm. LDC, STC(Rn) ANDC, ORC, XORC, LDC (#XX:8) Legend: Op : Operation field rn : Register field #imm. : immediate data Figure 2.9 System Control Instruction Codes 2.5.8 Block Data Transfer Instruction Table 2.11 describes the EEPMOV instruction. Figure 2.10 shows its object code format. Table 2.
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15 8 7 0 Op EEPROM Op Op: Operation field Figure 2.10 Block Data Transfer Instruction/EEPROM Write Operation Code Notes on EEPMOV Instruction Note 1 1. The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified by R5 to the address specified by R6. R5 → ← R6 R5 + R4L → ← R6 + R4L 2. When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not exceed H'FFFF.
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2.6 CPU States The CPU has three states: the program execution state, exception-handling state, and power-down state. The power-down state is further divided into three modes: the sleep mode, software standby mode, and hardware standby mode. Figure 2.11 summarizes these states, and figure 2.12 shows a map of the state transitions. State Program execution state The CPU executes successive program instructions. Exception-handling state A transient state triggered by a reset or interrupt.
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Program execution state Exception handing request SLEEP instruction SLEEP instruction with SSBY bit set Exception handing Exceptionhandling state Interrupt request NMI or IRQ0 to IRQ2 RES= 1 STBY= 1, RES= 0 Reset state Sleep mode Software standby mode Hardware standby mode Power-down state Notes: 1. A transition to the reset state occurs when RES goes Low, except when the chip is in the hardware standby mode. 2.
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2.6.3 Power-Down State The power-down state includes three modes: the sleep mode, the software standby mode, and the hardware standby mode. (1) Sleep Mode: The sleep mode is entered when a SLEEP instruction is executed. The CPU halts, but CPU register contents remain unchanged and the on-chip supporting modules continue to function.
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2.7 Access Timing and Bus Cycle The CPU is driven by the system clock (φ). The period from one rising edge of the system clock to the next is referred to as a “state.” Memory access is performed in a two- or three-state bus cycle. On-chip memory, on-chip supporting modules, and external devices are accessed in different bus cycles as described below. 2.7.1 Access to On-Chip Memory (RAM and ROM) On-chip ROM and RAM are accessed in a cycle of two states designated T1 and T2.
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Bus cycle T1 state T2 state Ø Address bus Address AS: High RD: High WR: High Data bus: high impedance state Figure 2.14 Pin States during On-Chip Memory Access Cycle Rev. 3.
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2.7.2 Access to On-Chip Register Field and External Devices The on-chip register field (I/O ports, dual-port RAM, on-chip supporting module registers, etc.) and external devices are accessed in a cycle consisting of three states: T1, T2, and T3. Only one byte of data can be accessed per cycle, via an 8-bit data bus. Access to word data or instruction codes requires two consecutive cycles (six states). Figure 2.15 shows the access cycle for the on-chip register field. Figure 2.
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Bus cycle T1 state T2 state T3 state Ø Address bus Address AS: High RD: High WR: High Data bus: high impedance state Figure 2.16 Pin States during On-Chip Register Field Access Cycle Rev. 3.
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Read cycle T1 state T2 state T3 state Ø Address bus Address AS RD WR: High Data bus Read data Figure 2.17 (a) External Device Access Timing (Read) Rev. 3.
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Write cycle T1 state T2 state T3 state Ø Address Address bus AS RD: High WR Write data Data bus Figure 2.17 (b) External Device Access Timing (Write) Rev. 3.
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Section 3 MCU Operating Modes and Address Space 3.1 Overview 3.1.1 Mode Selection The H8/338 Series operates in three modes numbered 1, 2, and 3. The mode is selected by the inputs at the mode pins (MD1 and MD0) when the chip comes out of a reset. See table 3.1. The ROMless versions of the H8/338 Series (HD6413388, HD6413378) can be used only in mode 1 (expanded mode with on-chip ROM disabled). Table 3.
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3.1.2 Mode and System Control Registers (MDCR and SYSCR) Table 3.2 lists the registers related to the chip’s operating mode: the system control register (SYSCR) and mode control register (MDCR). The mode control register indicates the inputs to the mode pins MD1 and MD0. Table 3.2 Mode and System Control Registers Name Abbreviation Read/Write Address System control register SYSCR R/W H'FFC4 Mode control register MDCR R H'FFC5 3.
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Bits 6 to 4Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the clock settling time when the chip recovers from the software standby mode by an external interrupt. During the selected time the CPU and on-chip supporting modules continue to stand by. These bits should be set according to the clock frequency so that the settling time is at least 10ms. For specific settings, see section 14.2, “System Control Register: Power-Down Control Bits.
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3.3 Mode Control Register (MDCR)H'FFC5 Bit: 7 6 5 4 3 2 1 0       MDS1 MDS0 Initial value: 1 1 1 0 0 1 * * Read/Write: R R R R R R R R Note: Initialized according to MD1 and MD0 inputs. The mode control register (MDCR) is an eight-bit register that indicates the operating mode of the chip. Bits 7 to 5Reserved: These bits cannot be modified and are always read as “1.” Bits 4 and 3Reserved: These bits cannot be modified and are always read as “0.
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3.4 Address Space Map Figures 3.1 to 3.3 show memory maps of the H8/338, H8/337, and H8/336 in modes 1, 2, and 3.
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Mode 1 Expanded Mode without On-Chip ROM H'0000 Mode 2 Expanded Mode with On-Chip ROM H'0000 Mode 3 Single-Chip Mode H'0000 Vector Table Vector Table Vector Table H'0047 H'0048 H'0047 H'0048 H'0047 H'0048 On-Chip ROM, 32k bytes On-Chip ROM, 32k bytes External Address Space H'7FFF H'7FFF H'8000 Reserved*1 H'BFFF H'C000 External Address Space H'F77F H'F780 H'F77F H'F780 Reserved*1,*2 H'FB7F H'FB80 H'FF7F H'FF80 H'FF87 H'FF88 Reserved*1,*2 H'FB7F H'FB80 On-Chip RAM*2, 1k byte External Address
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Mode 1 Expanded Mode without On-Chip ROM Mode 2 Expanded Mode with On-Chip ROM H'0000 H'0000 Vector Table Mode 3 Single-Chip Mode H'0000 Vector Table H'0047 H'0048 H'0047 H'0048 Vector Table H'0047 H'0048 On-Chip ROM, 24k bytes On-Chip ROM, 24k bytes H'5FFF H'6000 H'5FFF External Address Space Reserved*1 H'BFFF H'C000 External Address Space H'F77F H'F780 H'F77F H'F780 Reserved*1,*2 Reserved*1,*2 H'FB7F H'FB80 H'FF7F H'FF80 H'FF87 H'FF88 H'FB7F H'FB80 On-Chip RAM*2, 1k byte External Address
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Section 4 Exception Handling 4.1 Overview The H8/338 Series recognizes only two kinds of exceptions: interrupts and the reset. Table 4.1 indicates their priority and the timing of their hardware exception-handling sequence. Table 4.1 Hardware Exception-Handling Sequences and Priority Priority Type of Exception High Reset The hardware exception-handling sequence begins as soon as RES changes from Low to High.
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Figure 4.1 indicates the timing of the reset sequence in modes 2 and 3. Figure 4.2 indicates the timing in mode 1. Vector fetch Internal processing Instruction prefetch RES Ø Internal address bus (1) (2) (2) (3) Internal Read signal Internal Write signal Internal data bus (16 bits) (1) Reset vector address (H'0000) (2) Starting address of program (contents of H'0000 to H'0001) (3) First instruction of program Figure 4.1 Reset Sequence (Mode 2 or 3, Program Stored in on-chip ROM) Rev. 3.
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Figure 4.2 Reset Sequence (Mode 1) Rev. 3.
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4.2.3 Disabling of Interrupts after Reset After a reset, if an interrupt were to be accepted before initialization of the stack pointer (SP: R7), the program counter and condition code register might not be saved correctly, leading to a program crash. To prevent this, all interrupts, including NMI, are disabled immediately after a reset. The first program instruction is therefore always executed. This instruction should initialize the stack pointer (example: MOV.W #xx:16, SP). 4.3 Interrupts 4.3.
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Table 4.2 Interrupts Interrupt source No.
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4.3.2 Interrupt-Related Registers The interrupt-related registers are the system control register (SYSCR), IRQ sense control register (ISCR), and IRQ enable register (IER). Table 4.
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Bits 0 to 7IRQ0 to IRQ7 Sense Control (IRQ0SC to IRQ7SC): These bits determine whether IRQ0 to IRQ7 are level-sensed or sensed on the falling edge. Bits 0 to 7 IRQ0SC to IRQ7SC Description 0 An interrupt is generated when IRQ0 to IRQ7 inputs are Low. 1 An interrupt is generated by the falling edge of the IRQ0 to IRQ7 inputs.
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4.3.3 External Interrupts The nine external interrupts are NMI and IRQ0 to IRQ7. NMI, IRQ0, IRQ1, and IRQ2 can be used to recover from software standby mode. (1) NMI: A nonmaskable interrupt is generated on the rising or falling edge of the NMI input signal regardless of whether the I (interrupt mask) bit is set in the CCR. The valid edge is selected by the NMIEG bit in the system control register. The NMI vector number is 3.
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Interrupt controller NMI interrupt IRQ flag IRQ 0E CPU * Interrupt request IRQ0 interrupt Priority decision Vector number ADF ADIE ADI interrupt I (CCR) Note: * For edge-sensed interrupts, these AND gates change to the circuit shown below. IRQ0 flag IRQ0 edge IRQ0 E S Q IRQ0 interrupt Figure 4.3 Block Diagram of Interrupt Controller The IRQ interrupts and interrupts from the on-chip supporting modules all have corresponding enable bits.
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(1) An interrupt request is sent to the interrupt controller when an NMI interrupt occurs, and when an interrupt occurs on an IRQ input line or in an on-chip supporting module provided the enable bit of that interrupt is set to “1.” (2) The interrupt controller checks the I bit in the CCR and accepts the interrupt request if the I bit is cleared to “0.” If the I bit is set to “1” only NMI requests are accepted; other interrupt requests remain pending.
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Program execution Interrupt requested? No Yes Yes NMI? No No Pending I = 0? Yes No IRQ 0? Yes No IRQ 1? Yes ADI? Yes Latch vector No. Save PC Save CCR Reset I 1 Read vector address Branch to software interrupt-handling routine Figure 4.4 Hardware Interrupt-Handling Sequence Rev. 3.
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SP-4 SP(R7) CCR SP-3 SP+1 CCR* SP-2 SP+2 PCH SP-1 SP+3 PCL SP+4 SP(R7) Even address Stack area Before interrupt is accepted Legend: PCH PCL CCR SP Pushed onto stack After interrupt is accepted Program counter (upper byte) Program counter (lower byte) Condition code register Stack pointer Notes: 1. The PC contains the address of the first instruction executed after return. 2. Registers must be saved and restored by word access at an even address. * Ignored on return. Figure 4.
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Rev. 3.0, 09/98, page 73 of 361 Figure 4.6 Timing of Interrupt Sequence Interrupt priority decision. Wait for end of instruction.
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4.3.6 Interrupt Response Time Table 4.4 indicates the number of states that elapse from an interrupt request signal until the first instruction of the software interrupt-handling routine is executed. Since on-chip memory is accessed 16 bits at a time, very fast interrupt service can be obtained by placing interrupt-handling routines in on-chip ROM and the stack in on-chip RAM. Table 4.4 Number of States before Interrupt Service Number of States No.
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4.3.7 Precaution Note that the following type of contention can occur in interrupt handling. Contention between Interrupt Request and Disable: When software clears the enable bit of an interrupt to “0” to disable the interrupt, the interrupt becomes disabled after execution of the clearing instruction.
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4.4 Note on Stack Handling In word access, the least significant bit of the address is always assumed to be 0. The stack is always accessed by word access. Care should be taken to keep an even value in the stack pointer (general register R7). Use the PUSH and POP (or MOV.W Rn, @−SP and MOV.W @SP+, Rn) instructions to push and pop registers on the stack. Setting the stack pointer to an odd value can cause programs to crash. Figure 4.
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Section 5 Clock Pulse Generator 5.1 Overview The H8/338 Series has a built-in clock pulse generator (CPG) consisting of an oscillator circuit, a system (φ) clock divider, and a prescaler. The prescaler generates clock signals for the on-chip supporting modules. 5.1.1 Block Diagram CPG XTAL EXTAL Oscillator circuit Divider 2 Prescaler Ø Ø/2 to Ø/4096 Figure 5.1 Block Diagram of Clock Pulse Generator Rev. 3.
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5.2 Oscillator Circuit If an external crystal is connected across the EXTAL and XTAL pins, the on-chip oscillator circuit generates a clock signal for the system clock divider. Alternatively, an external clock signal can be applied to the EXTAL pin. (1) Connecting an External Crystal ① Circuit Configuration: An external crystal can be connected as in the example in figure 5.2. An AT-cut parallel resonating crystal should be used. CL1 EXTAL XTAL CL2 CL1 = CL2 = 10 to 22pF Figure 5.
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③ Note on Board Design: When an external crystal is connected, other signal lines should be kept away from the crystal circuit to prevent induction from interfering with correct oscillation. See figure 5.4. The crystal and its load capacitors should be placed as close as possible to the XTAL and EXTAL pins. Not allowed Signal A Signal B H8/337 CL2 XTAL EXTAL CL1 (Example of H8/337) Figure 5.4 Notes on Board Design around External Crystal Rev. 3.
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(2) Input of External Clock Signal ① Circuit Configuration: An external clock signal can be input as shown in the examples in figure 5.5. In example (b) in figure 5.5, the external clock signal should be kept high during standby. EXTAL External clock input XTAL Open (a) EXTAL External clock input 74HC04 XTAL (b) Figure 5.5 External Clock Input (Example) ② External Clock Input Frequency Double the system clock (φ) frequency Duty factor 45% to 55% 5.
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Section 6 I/O Ports 6.1 Overview The H8/338 Series has nine parallel I/O ports, including: • Six 8-bit input/output ports-ports 1, 2, 3, 4, 6, and 9 • One 8-bit input port-port 7 • One 7-bit input/output port-port 8 • One 3-bit input/output port-port 5 Ports 1, 2, and 3 have programmable input pull-up transistors. Ports 1 to 6, 8, and 9 can drive a Darlington pair. Ports 1 to 4, 6, and 9 can drive one TTL load and a 90pF capacitive load. Ports 5 and 8 can drive one TTL load and a 30pF capacitive load.
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Table 6.
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Table 6.
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6.2 Port 1 Port 1 is an 8-bit input/output port that also provides the low bits of the address bus. The function of port 1 depends on the MCU mode as indicated in table 6.2. Table 6.
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Port 1 Data Register (P1DR)H'FFB2 Bit: 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P13 P12 P11 P10 Initial value: 0 0 0 0 0 0 0 0 Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W P1DR is an 8-bit register containing the data for pins P17 to P10. When the CPU reads P1DR, for output pins it reads the value in the P1DR latch, but for input pins, it obtains the logic level directly from the pin, bypassing the P1DR latch.
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Input Pull-Up Transistors: Port 1 has built-in programmable input pull-up transistors that are available in modes 2 and 3. The pull-up for each bit can be turned on and off individually. To turn on an input pull-up in mode 2 or 3, set the corresponding P1PCR bit to “1” and clear the corresponding P1DDR bit to “0.” P1PCR is cleared to H'00 by a reset and in the hardware standby mode, turning all input pull-ups off. In software standby mode, the previous state is maintained. Table 6.
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Figure 6.1 shows a schematic diagram of port 1. Reset R D Q P1 n PCR C Mode 1 Reset S Q R D P1 n DDR C WP1D Reset Mode 3 R D Q P1 n * Internal address bus Hardware standby Internal data bus WP1P RP1P P1 n DR C Mode 1 or 2 WP1 RP1 WP1P: Write Port 1 PCR WP1D: Write Port 1 DDR WP1: Write Port 1 RP1P : Read Port 1 PCR RP1: Read Port 1 n = 0 to 7 Note: * Set-priority Figure 6.1 Port 1 Schematic Diagram Rev. 3.
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6.3 Port 2 Port 2 is an 8-bit input/output port that also provides the high bits of the address bus. The function of port 2 depends on the MCU mode as indicated in table 6.5. Table 6.
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Port 2 Data Register (P2DR)H'FFB3 Bit: 7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21 P20 Initial value: 0 0 0 0 0 0 0 0 Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W P2DR is an 8-bit register containing the data for pins P27 to P20. When the CPU reads P2DR, for output pins it reads the value in the P2DR latch, but for input pins, it obtains the logic level directly from the pin, bypassing the P2DR latch.
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Input Pull-Up Transistors: Port 2 has built-in programmable input pull-up transistors that are available in modes 2 and 3. The pull-up for each bit can be turned on and off individually. To turn on an input pull-up in mode 2 or 3, set the corresponding P2PCR bit to “1” and clear the corresponding P2DDR bit to “0.” P2PCR is cleared to H'00 by a reset and in the hardware standby mode, turning all input pull-ups off. In software standby mode, the previous state is maintained. Table 6.
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Figure 6.2 shows a schematic diagram of port 2. Reset R D Q P2 n PCR C WP2P Mode 1 Reset S Q R D P2n DDR C WP2D Reset Mode 3 R D Q P2 n P2 n DR C Mode 1 or 2 * Internal address bus Hardware standby Internal data bus RP2P WP2 RP2 WP2P: Write Port 2 PCR WP2D: Write Port 2 DDR WP2: Write Port 2 RP2P : Read Port 2 PCR RP2: Read Port 2 n = 0 to 7 Note: * Set-priority Figure 6.2 Port 2 Schematic Diagram Rev. 3.
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6.4 Port 3 Port 3 is an 8-bit input/output port that also provides the external data bus. The function of port 3 depends on the MCU mode as indicated in table 6.8. Table 6.8 Functions of Port 3 Mode 1 Mode 2 Mode 3 Data bus Data bus Input/output port Pins of port 3 can drive a single TTL load and a 90pF capacitive load when they are used as output pins. They can also drive a Darlington pair. When they are used as input pins, they have programmable MOS transistor pull-ups. Table 6.
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P3DR is an 8-bit register containing the data for pins P37 to P30. When the CPU reads P3DR, for output pins it reads the value in the P3DR latch, but for input pins, it obtains the logic level directly from the pin, bypassing the P3DR latch.
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Table 6.10 indicates the states of the input pull-up transistors in each operating mode. Table 6.10 States of Input Pull-Up Transistors (Port 3) Mode Reset Hardware Standby Software Standby Other Operating Modes 1 Off Off Off Off 2 Off Off Off Off 3 Off Off On/off On/off Notes: Off: The input pull-up transistor is always off. On/off: The input pull-up transistor is on if P3PCR = “1” and P3DDR = “0,” but off otherwise. Rev. 3.
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Figure 6.3 shows a schematic diagram of port 3. Reset Mode 3 R D Q P3 n PCR C RP3P WP3P Mode 3 Reset R D Q External address write WP3D Mode 3 Reset R D Q P3 n Internal data bus P3 n DDR C P3 n DR C Mode 1 or 2 WP3 RP3 External address read WP3P: Write Port 3 PCR WP3D: Write Port 3 DDR WP3: Write Port 3 RP3P : Read Port 3 PCR RP3: Read Port 3 n = 0 to 7 Figure 6.3 Port 3 Schematic Diagram Rev. 3.
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6.5 Port 4 Port 4 is an 8-bit input/output port that also provides the input and output pins for the 8-bit timers and the output pins for the PWM timers. The pin functions depend on control bits in the control registers of the timers. Pins not used by the timers are available for general-purpose input/output. Table 6.11 lists the pin functions, which are the same in both the expanded and single-chip modes. Table 6.
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Port 4 Data Register (P4DR)H'FFB7 Bit: 7 6 5 4 3 2 1 0 P47 P46 P45 P44 P43 P42 P41 P40 Initial value: 0 0 0 0 0 0 0 0 Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W P4DR is an 8-bit register containing the data for pins P47 to P40. When the CPU reads P4DR, for output pins (P4DDR = “1”) it reads the value in the P4DR latch, but for input pins (P4DDR = “0”), it obtains the logic level directly from the pin, bypassing the P4DR latch.
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Figures 6.4 (a) and 6.4 (b) show schematic diagrams of port 4. Reset R D Q P4 n DDR P4 n R D Q P4 n DR C Internal data bus C WP4D Reset WP4 RP4 8-bit timer module Counter reset input Counter clock input WP4D: Write Port 4 DDR WP4: Write Port 4 RP4: Read Port 4 n = 0, 2, 3, 5 Figure 6.4 (a) Port 4 Schematic Diagram (Pins P40, P42, P43, and P45) Rev. 3.
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Reset R D Q WP4D Reset R D Q P4 n P4 n DR C WP4 Internal data bus P4 n DDR C 8-bit timer module, PWM timer module Output enable 8-bit timer output or PWM timer output RP4 WP4D: Write Port 4 DDR WP4: Write Port 4 RP4: Read Port 4 n = 1, 4, 6, 7 Figure 6.4 (b) Port 4 Schematic Diagram (Pins P41, P44, P46, and P47) Rev. 3.
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6.6 Port 5 Port 5 is a 3-bit input/output port that also provides the input and output pins for serial communication interface 0 (SCI0). The pin functions depend on control bits in the serial control register (SCR). Pins not used for serial communication are available for general-purpose input/output. Table 6.13 lists the pin functions, which are the same in both the expanded and single-chip modes. Table 6.
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Port 5 Data Register (P5DR)H'FFBA Bit: 7 6 5 4 3 2 1 0      P52 P51 P50 Initial value: 1 1 1 1 1 0 0 0 Read/Write:      R/W R/W R/W P5DR is an 8-bit register containing the data for pins P52 to P50. When the CPU reads P5DR, for output pins (P5DDR = “1”) it reads the value in the P5DR latch, but for input pins (P5DDR = “0”), it obtains the logic level directly from the pin, bypassing the P5DR latch. This also applies to pins used for serial communication.
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Figures 6.5 (a) to 6.5 (c) show schematic diagrams of port 5. Reset R D Q WP5D Reset R D Q P5 0 P5 0 DR C Internal data bus P5 0 DDR C WP5 SCI module Transmit enable Transmit data RP5 WP5D: WP5: RP5: Write Port 5 DDR Write Port 5 Read Port 5 Figure 6.5 (a) Port 5 Schematic Diagram (Pin P50) Rev. 3.
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Reset R D Q P5 1DDR C SCI module WP5D P5 1 R D Q P5 1 DR C Internal data bus Receive enable Reset WP5 RP5 Receive data WP5D: WP5: RP5: Write Port 5 DDR Write Port 5 Read Port 5 Figure 6.5 (b) Port 5 Schematic Diagram (Pin P51) Rev. 3.
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Reset R D Q P5 2 DDR C SCI module WP5D R D Q P5 2 P5 2 DR C Clock input enable Internal data bus Reset WP5 Clock output enable Clock output RP5 Clock input WP5D: WP5: RP5: Write Port 5 DDR Write Port 5 Read Port 5 Figure 6.5 (c) Port 5 Schematic Diagram (Pin P52) Rev. 3.
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6.7 Port 6 Port 6 is an 8-bit input/output port that also provides the input and output pins for the free-running timer and the IRQ6 and IRQ7 input/output pins. The pin functions depend on control bits in the free-running timer control registers, and on bit 6 or 7 of the interrupt enable register. Pins not used for timer or interrupt functions are available for general-purpose input/output. Table 6.15 lists the pin functions, which are the same in both the expanded and single-chip modes. Table 6.
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Port 6 Data Register (P6DR)H'FFBB Bit: 7 6 5 4 3 2 1 0 P67 P66 P65 P64 P63 P62 P61 P60 Initial value: 0 0 0 0 0 0 0 0 Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W P6DR is an 8-bit register containing the data for pins P67 to P60. When the CPU reads P6DR, for output pins (P6DDR = “1”) it reads the value in the P6DR latch, but for input pins (P6DDR = “0”), it obtains the logic level directly from the pin, bypassing the P6DR latch.
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Figures 6.6 (a) to 6.6 (d) shows schematic diagrams of port 6. Reset R D Q WP6D Reset P6 n R D Q P6 n DR C Internal data bus P6 n DDR C WP6 RP6 Free-running timer module WP6D: Write Port 6 DDR WP6: Write Port 6 RP6: Read Port 6 n = 0, 2 - 5 Input capture input, counter clock input Figure 6.6 (a) Port 6 Schematic Diagram (Pins P60, P62, P63, P64, and P65) Rev. 3.
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Reset R D Q P6 1 DDR WP6D Reset R D Q P6 1 P6 1 DR Internal data bus C C WP6 Free-running timer module Output enable Output-compare output RP6 WP6D: WP6: RP6: Write Port 6 DDR Write Port 6 Read Port 6 Figure 6.6 (b) Port 6 Schematic Diagram (Pin P61) Rev. 3.
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Reset R D Q WP6D Reset R D Q P6 6 P6 6 DR C Internal data bus P6 6 DDR C Free-running timer module WP6 Output enable Output-compare output RP6 IRQ6 input IRQ6 enable register WP6D: WP6: RP6: Write Port 6 DDR Write Port 6 Read Port 6 IRQ6 enable Figure 6.6 (c) Port 6 Schematic Diagram (Pin P66) Rev. 3.
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Reset R D Q WP6D Reset P67 R D Q P6 7 DR Internal data bus P6 7 DDR C C WP6 RP6 IRQ7 input WP6D: Write Port 6 DDR WP6: Write Port 6 RP6: Read Port 6 IRQ enable register IRQ7 enable Figure 6.6 (d) Port 6 Schematic Diagram (Pin P67) Rev. 3.
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6.8 Port 7 Port 7 is an 8-bit input port that also provides the analog input pins for the A/D converter module, and analog output pins for the D/A converter module. The pin functions are the same in both the expanded and single-chip modes. Table 6.17 lists the pin functions. Table 6.18 describes the port 7 data register, which simply consists of connections of the port 7 pins to the internal data bus. Figure 6.7 (a) and 6.7 (b) show schematic diagrams of port 7. Table 6.
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P7n Internal data bus RP7 A/D converter module Analog input RP7: Read port 7 n = 0 to 5 Figure 6.7 (a) Port 7 Schematic Diagram (Pins P70 to P75) Internal data bus RP7 P7n A/D converter module Analog input D/A converter module RP7: Read port 7 n = 6 or 7 Output enable Analog output Figure 6.7 (b) Port 7 Schematic Diagram (Pins P76 and P77) Rev. 3.
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6.9 Port 8 Port 8 is a 7-bit input/output port that also provides pins for interrupt input and serial communication. Table 6.19 lists the pin functions. Table 6.
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Port 8 Data Register (P8DR)H'FFBF Bit: 7 6 5 4 3 2 1 0  P86 P85 P84 P83 P82 P81 P80 Initial value: 1 0 0 0 0 0 0 0 Read/Write:  R/W R/W R/W R/W R/W R/W R/W P8DR is an 8-bit register containing the data for pins P86 to P80. When the CPU reads P8DR, for output pins (P8DDR = “1”) it reads the value in the P8DR latch, but for input pins (P8DDR = “0”), it obtains the logic level directly from the pin, bypassing the P8DR latch.
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Figures 6.8 (a) to 6.8 (d) show schematic diagrams of port 8. Reset R D Q P8 n DDR C P8 n R D Q P8 n DR C WP8 Internal data bus WP8D Reset RP8 WP8D: Write Port 8 DDR WP8: Write Port 8 RP8: Read Port 8 n = 0 to 3 Figure 6.8 (a) Port 8 Schematic Diagram (Pins P80 to P83) Rev. 3.
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Reset R D Q P8 4 DDR WP8D Reset R D Q P8 4 P8 4 DR Internal data bus C C WP8 SCI module Transmit enable Transmit data RP8 IRQ3 input IRQ enable register WP8D: WP8: RP8: Write Port 8 DDR Write Port 8 Read Port 8 Figure 6.8 (b) Port 8 Schematic Diagram (Pin P84) Rev. 3.
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Reset R D Q P8 5 DDR C SCI module WP8D P8 5 R D Q P8 5 DR C Internal data bus Receive enable Reset WP8 RP8 Receive data IRQ4 input IRQ enable register WP8D: Write Port 8 DDR WP8: Write Port 8 RP8: Read Port 8 IRQ4 enable Figure 6.8 (c) Port 8 Schematic Diagram (Pin P85) Rev. 3.
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Reset R D Q P8 6 DDR C SCI module WP8D Clock input enable R D Q P8 6 P8 6 DR C Internal data bus Reset WP8 Clock output enable Clock output RP8 Clock input IRQ5 input IRQ enable register WP8D: WP8: RP8: Write Port 8 DDR Write Port 8 Read Port 8 Figure 6.8 (d) Port 8 Schematic Diagram (Pin P86) Rev. 3.
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6.10 Port 9 Port 9 is an 8-bit input/output port that also provides pins for interrupt input (IRQ0 to IRQ2), A/D trigger input, system clock (φ) output, and bus control signals (in the expanded modes). Pins P97 to P93 have different functions in different modes. Pins P92 to P90 have the same functions in all modes. Table 6.21 lists the pin functions. Table 6.
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Port 9 Data Direction Register (P9DDR)H'FFC0 Bit 7 6 5 4 3 2 1 0 P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR Modes 1 and 2 Initial value 0 1 0 0 0 0 0 0 Read/Write W  W W W W W W Mode 3 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W P9DDR is an 8-bit register that selects the direction of each pin in port 9. A pin functions as an output pin if the corresponding bit in P9DDR is set to “1,” and as in input pin if the bit is cleared to “0.
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Pin P97: In modes 1 and 2, this pin is used for input of the WAIT bus control signal. It is unaffected by the values in P9DDR and P9DR. In mode 3 (single-chip mode), this pin can be used for general-purpose input or output. Reset: In the single-chip mode (mode 3), a reset initializes all pins of port 9 to the generalpurpose input function.
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Figures 6.9 (a) to 6.9 (e) show schematic diagrams of port 9. Reset R D Q P9 0 DDR C P9 0 R D Q P9 0 DR C Internal data bus WP9D Reset WP9 RP9 A/D converter module ADTRG IRQ2 input WP9D: WP9: RP9: Write Port 9 DDR Write Port 9 Read Port 9 IRQ enable register IRQ2 enable Figure 6.9 (a) Port 9 Schematic Diagram (Pin P90) Rev. 3.
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Reset R D Q P9 n DDR C P9 n R D Q P9 n DR C Internal data bus WP9D Reset WP9 RP9 WP9D: Write Port 9 DDR WP9: Write Port 9 RP9: Read Port 9 n = 1, 2 IRQ0 input IRQ1 input IRQ enable register IRQ0 enable IRQ1 enable Figure 6.9 (b) Port 9 Schematic Diagram (Pins P91 and P92) Rev. 3.
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Hardware standby Mode 1 or 2 Reset R D Q P9 n DDR WP9D Reset Mode 3 R D Q P9 n P9 n DR Internal data bus C C Mode 1 or 2 WP9 RP9 WP9D: Write Port 9 DDR WP9: Write Port 9 RP9: Read Port 9 n = 3, 4, 5 Figure 6.9 (c) Port 9 Schematic Diagram (Pins P93, P94, and P95) Rev. 3.
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Hardware standby Reset Mode 1, 2 S Q R D P9 6DDR C * Internal data bus WP9D Ø P96 RP9 WP9D: Write Port 9 DDR WP9: Write Port 9 RP9: Read Port 9 Note: * Set-priority Figure 6.9 (d) Port 9 Schematic Diagram (Pin P96) Rev. 3.
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Reset Mode 1 or 2 R D Q P9 7DDR C Reset P9 7 R D Q P9 7 DR C Internal data bus WP9D WP9 RP9 WAIT input WP9D: WP9: RP9: Write Port 9 DDR Write Port 9 Read Port 9 Figure 6.9 (e) Port 9 Schematic Diagram (Pin P97) Rev. 3.
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Section 7 16-Bit Free-Running Timer 7.1 Overview The H8/338 Series has an on-chip 16-bit free-running timer (FRT) module that uses a 16-bit freerunning counter as a time base. Applications of the FRT module include rectangular-wave output (up to two independent waveforms), input pulse width measurement, and measurement of external clock periods. 7.1.1 Features The features of the free-running timer module are listed below.
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External clock source Internal clock sources Ø/2 Ø/8 FTCI Ø/32 Clock Clock select CORA (H/L) Compare-match A Comparator A FTOA Bus interface Overflow FTOB FRC (H/L) Clear Comparator B FTIA FTIB FTIC OCRB (H/L) Control logic Capture FTID ICRA (H/L) ICRB (H/L) Module data bus Comparematch B ICRC (H/L) ICRD (H/L) TCSR TIER TCR TOCR ICIA ICIB ICIC ICID OCIA OCIB FOVI Legend: OCRA, B FRC ICRA to D TCSR TIER TCR TOCR Interrupt signals Free-Running Counter (16 bits) Output Compare Register A, B
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7.1.3 Input and Output Pins Table 7.1 lists the input and output pins of the free-running timer module. Table 7.
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Table 7.2 Register Configuration (cont) Name Abbreviation R/W Initial Value Address Input capture register B (High) ICRB (H) R H'00 H'FF9A Input capture register B (Low) ICRB (L) R H'00 H'FF9B Input capture register C (High) ICRC (H) R H'00 H'FF9C Input capture register C (Low) ICRC (L) R H'00 H'FF9D Input capture register D (High) ICRD (H) R H'00 H'FF9E Input capture register D (Low) ICRD (L) R H'00 H'FF9F 7.2 Register Descriptions 7.2.
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7.2.2 Output Compare Registers A and B (OCRA and OCRB)H'FF94 Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W OCRA and OCRB are 16-bit readable/writable registers, the contents of which are continually compared with the value in the FRC.
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Input capture can be buffered by using the input capture registers in pairs. When the BUFEA bit in the timer control register (TCR) is set to “1,” ICRC is used as a buffer register for ICRA as shown in figure 7.2. When an FTIA input is received, the old ICRA contents are moved into ICRC, and the new FRC count is copied into ICRA.
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Table 7.3 Buffered Input Capture Edge Selection (Example) IEDGA IEDGC Input Capture Edge 0 0 Captured on falling edge of input capture A (FTIA) 0 1 Captured on both rising and falling edges of input capture A (FTIA) 1 0 1 1 (Initial value) Captured on rising edge of input capture A (FTIA) Because the input capture registers are 16-bit registers, a temporary register (TEMP) is used when they are read. See section 7.3, “CPU Interface,” for details.
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7.2.4 Timer Interrupt Enable Register (TIER)-H'FF90 Bit: 7 6 5 4 3 2 1 0 ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE  Initial value: 0 0 0 0 0 0 0 1 Read/Write: R/W R/W R/W R/W R/W R/W R/W  The TIER is an 8-bit readable/writable register that enables and disables interrupts. The TIER is initialized to H'01 (all interrupts disabled) at a reset and in the standby modes.
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Bit 4Input Capture Interrupt D Enable (ICIDE): This bit selects whether to request input capture interrupt D (ICID) when input capture flag D (ICFD) in the timer status/control register (TCSR) is set to “1.” Bit 4 ICIDE Description 0 Input capture interrupt request D (ICID) is disabled. 1 Input capture interrupt request D (ICID) is enabled.
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7.2.5 Timer Control/Status Register (TCSR)H'FF91 Bit: 7 6 5 4 3 2 1 0 ICFA ICFB ICFC ICFD OCFA OCFB OVF CCLRA Initial value: 0 0 0 0 0 0 0 0 Read/Write: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/W The TCSR is an 8-bit readable and partially writable* register that contains the seven interrupt flags and specifies whether to clear the counter on compare-match A (when the FRC and OCRA values match).
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Bit 6Input Capture Flag B (ICFB): This status bit is set to “1” to flag an input capture B event. If BUFEB = “0,” ICFB indicates that the FRC value has been copied to ICRB. If BUFEB = “1,” ICFB indicates that the old ICRB value has been moved into ICRD and the new FRC value has been copied to ICRB. ICFB must be cleared by software. It is set by hardware, however, and cannot be set by software.
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Bit 3Output Compare Flag A (OCFA): This status flag is set to “1” when the FRC value matches the OCRA value. This flag must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 3 OCFA Description 0 To clear OCFA, the CPU must read OCFA after it has been set to “1,” then write a “0” in this bit. 1 This bit is set to 1 when FRC = OCRA. (Initial value) Bit 2Output Compare Flag B (OCFB): This status flag is set to “1” when the FRC value matches the OCRB value.
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7.2.6 Timer Control Register (TCR)-H'FF96 Bit: 7 6 5 4 3 2 1 0 IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0 Initial value: 0 0 0 0 0 0 0 0 Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W The TCR is an 8-bit readable/writable register that selects the rising or falling edge of the input capture signals, enables the input capture buffer mode, and selects the FRC clock source. The TCR is initialized to H'00 at a reset and in the standby modes.
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Bit 4Input Edge Select D (IEDGD): This bit causes input capture D events to be recognized on the selected edge of the input capture D signal (FTID). Bit 4 IEDGD Description 0 Input capture D events are recognized on the falling edge of FTID. 1 Input capture D events are recognized on the rising edge of FTID. (Initial value) Bit 3Buffer Enable A (BUFEA): This bit selects whether to use ICRC as a buffer register for ICRA. Bit 3 BUFEA Description 0 ICRC is used for input capture C.
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7.2.7 Timer Output Compare Control Register (TOCR)H'FF97 Bit: 7 6 5 4 3 2 1 0    OCRS OEA OEB OLVLA OLVLB Initial value: 1 1 1 0 0 0 0 0 Read/Write:    R/W R/W R/W R/W R/W The TOCR is an 8-bit readable/writable register that controls the output compare function. The TOCR is initialized to H'E0 at a reset and in the standby modes. Bits 7 to 5Reserved: These bits cannot be modified and are always read as “1.
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Bit 1Output Level A (OLVLA): This bit selects the logic level to be output at the FTOA pin when the FRC and OCRA values match. Bit 1 OLVLA Description 0 A “0” logic level (Low) is output for compare-match A. 1 A “1” logic level (High) is output for compare-match A. (Initial value) Bit 0Output Level B (OLVLB): This bit selects the logic level to be output at the FTOB pin when the FRC and OCRB values match. Bit 0 OLVLB Description 0 A “0” logic level (Low) is output for compare-match B.
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7.3 CPU Interface The free-running counter (FRC), output compare registers (OCRA and OCRB), and input capture registers (ICRA to ICRD) are 16-bit registers, but they are connected to an 8-bit data bus. When the CPU accesses these registers, to ensure that both bytes are written or read simultaneously, the access is performed using an 8-bit temporary register (TEMP).
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(1) Upper byte write Module data bus CPU writes data H'AA Bus interface TEMP [H'AA] FRC H [ ] FRC L [ ] (2) Lower byte write CPU writes data H'55 Module data bus Bus interface TEMP [H'AA] FRC H [H'AA] FRC L [H'55] Figure 7.3 (a) Write Access to FRC (when CPU writes H'AA55) Rev. 3.
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(1) Upper byte read Module data bus CPU reads data H'AA Bus interface TEMP [H'55] FRC H [H'AA] FRC L [H'55] (2) Lower byte read CPU reads data H'55 Module data bus Bus interface TEMP [H'55] FRC H [ ] FRC L [ ] Figure 7.3 (b) Read Access to FRC (when FRC contains H'AA55) Rev. 3.
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7.4 Operation 7.4.1 FRC Incrementation Timing The FRC increments on a pulse generated once for each period of the selected (internal or external) clock source. The clock source is selected by bits CKS0 and CKS1 in the TCR. Internal Clock: The internal clock sources (φ/2, φ/8, φ/32) are created from the system clock (φ) by a prescaler. The FRC increments on a pulse generated from the falling edge of the prescaler output. See figure 7.4. Ø Internal clock FRC clock pulse FRC N-1 N N+1 Figure 7.
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Ø FTCI FRC clock pulse N FRC N+1 Figure 7.5 Increment Timing for External Clock Source Ø FRC OCRA N+1 N N N N+1 N Internal comparematch A signal Clear* OLVLA FTOA Note: * Cleared by software Figure 7.6 Minimum External Clock Pulse Width Rev. 3.
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7.4.2 Output Compare Timing (1) Setting of Output Compare Flags A and B (OCFA and OCFB): The output compare flags are set to “1” by an internal compare-match signal generated when the FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the last state in which the two values match, just before the FRC increments to a new value. Accordingly, when the FRC and OCR values match, the compare-match signal is not generated until the next period of the clock source. Figure 7.
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(3) FRC Clear Timing: If the CCLRA bit in the TCSR is set to “1,” the FRC is cleared when compare-match A occurs. Figure 7.9 shows the timing of this operation. Read cycle: CPU reads upper byte of ICR T1 T2 T3 Ø Input at FTI pin Internal input capture signal Figure 7.9 Clearing of FRC by Compare-Match A 7.4.
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If the upper byte of ICRA/B/C/D is being read when the corresponding input capture signal arrives, the internal input capture signal is delayed by one state. Figure 7.11 shows the timing for this case. Read cycle: CPU reads upper byte of ICRA or ICRC T1 T2 T3 Ø Input at FTIA pin Internal input capture signal Figure 7.11 Input Capture Timing (1-State delay) In buffer mode, this delay occurs if the CPU is reading either of the two registers concerned.
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Figure 7.13 shows how input capture operates when ICRA and ICRC are used in buffer mode and IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDGA = 1 and IEDGC = 0), so that input capture is performed on both the rising and falling edges of FTIA. Ø FRC N OCRA or B N N+1 Internal comparematch signal OCFA or B Figure 7.13 Buffered Input Capture with Both Edges Selected In this mode, input capture does not cause the FRC contents to be copied to ICRC.
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7.4.4 Setting of FRC Overflow Flag (OVF) The FRC overflow flag (OVF) is set to “1” when the FRC overflows (changes from H'FFFF to H'0000). Figure 7.15 shows the timing of this operation. FRC Clear counter 6 H'FFFF OCRA OCRB H'0000 FTOA FTOB Figure 7.15 Setting of Overflow Flag (OVF) 7.5 Interrupts The free-running timer can request seven types of interrupts: input capture A to D (ICIA, ICIB, ICIC, ICID), output compare A and B (OCIA and OCIB), and overflow (FOVI).
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7.6 Sample Application In the example below, the free-running timer is used to generate two square-wave outputs with a 50% duty cycle and arbitrary phase relationship. The programming is as follows: (1) The CCLRA bit in the TCSR is set to “1.” (2) Each time a compare-match interrupt occurs, software inverts the corresponding output level bit in TOCR (OLVLA or OLVLB).
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7.7 Application Notes Application programmers should note that the following types of contention can occur in the freerunning timers. (1) Contention between FRC Write and Clear: If an internal counter clear signal is generated during the T3 state of a write cycle to the lower byte of the free-running counter, the clear signal takes priority and the write is not performed. Figure 7.17 shows this type of contention.
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Figure 7.18 shows this type of contention. Write cycle: CPU write to lower byte of OCRA or OCRB T1 T2 T3 Ø OCR address Internal address bus Internal write signal FRC N OCRA or OCRB N N+1 M Write data Compare-match A or B signal Inhibited Figure 7.
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(4) Incrementation Caused by Changing of Internal Clock Source: When an internal clock source is changed, the changeover may cause the FRC to increment. This depends on the time at which the clock select bits (CKS1 and CKS0) are rewritten, as shown in table 7.5. The pulse that increments the FRC is generated at the falling edge of the internal clock source. If clock sources are changed when the old source is High and the new source is Low, as in case No. 3 in table 7.
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Table 7.5 Effect of Changing Internal Clock Sources (cont) No. Description 3 High → Low: CKS1 and CKS0 are rewritten while old clock source is High and new clock source is Low. Timing chart Old clock source New clock source * FRC clock pulse FRC N N +1 N +2 CKS rewrite 4 High → High: CKS1 and CKS0 are rewritten while both clock sources are High.
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Section 8 8-Bit Timers 8.1 Overview The H8/338 Series includes an 8-bit timer module with two channels (TMR0 and TMR1). Each channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that are constantly compared with the TCNT value to detect compare-match events. One application of the 8-bit timer module is to generate a rectangular-wave output with an arbitrary duty cycle. 8.1.1 Features The features of the 8-bit timer module are listed below.
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8.1.2 Block Diagram Figure 8.1 shows a block diagram of one channel in the 8-bit timer module. The other channel is identical.
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8.1.3 Input and Output Pins Table 8.1 lists the input and output pins of the 8-bit timer. Table 8.1 Input and Output Pins of 8-Bit Timer Abbreviation Name TMR0 TMR1 I/O Function Timer output TMO0 TMO1 Output Output controlled by compare-match Timer clock input TMCI0 TMCI1 Input External clock source for the counter Timer reset input TMRI0 TMRI1 Input External reset signal for the counter 8.1.4 Register Configuration Table 8.2 lists the registers of the 8-bit timer module.
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8.2 Register Descriptions 8.2.1 Timer Counter (TCNT)H'FFCC (TMR0), H'FFD4 (TMR1) Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W Each timer counter (TCNT) is an 8-bit up-counter that increments on a pulse generated from an internal or external clock source selected by clock select bits 2 to 0 (CKS2 to CKS0) of the timer control register (TCR). The CPU can always read or write the timer counter.
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Compare-match is not detected during the T3 state of a write cycle to TCORA or TCORB. See item (3) in section 8.6, “Application Notes.” 8.2.
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Bit 5Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a timer overflow interrupt (OVI) when the overflow flag (OVF) in the timer control/status register (TCSR) is set to “1.” Bit 5 OVIE Description 0 The timer overflow interrupt request (OVI) is disabled. 1 The timer overflow interrupt request (OVI) is enabled.
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Bits 2, 1, and 0Clock Select (CKS2, CKS1, and CKS0): These bits and bits ICKS1 and ICKS0 in the serial/timer control register (STCR) select the internal or external clock source for the timer counter. Six internal clock sources, derived by prescaling the system clock, are available for each timer channel. For internal clock sources the counter is incremented on the falling edge of the internal clock.
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8.2.4 Timer Control/Status Register (TCSR)H'FFC9 (TMR0), H'FFD1 (TMR1) Bit: 7 6 5 4 3 2 1 0 CMFB CMFA OVF  OS3 OS2 OS1 OS0 Initial value: 0 0 0 1 0 0 0 0 Read/Write: R/(W)* R/(W)* R/(W)*  R/W R/W R/W R/W Note: Software can write a “0” in bits 7 to 5 to clear the flags, but cannot write a “1” in these bits.
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Bit 5Timer Overflow Flag (OVF): This status flag is set to “1” when the timer count overflows (changes from H'FF to H'00). OVF must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 5 OVF Description 0 To clear OVF, the CPU must read OVF after it has been set to “1,” then write a “0” in this bit. 1 This bit is set to 1 when TCNT changes from H'FF to H'00. (Initial value) Bit 4Reserved: This bit is always read as “1.” It cannot be written.
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8.2.5 Serial/Timer Control Register (STCR)H'FFC3 Bit: 7 6 5 4 3 2 1 0      MPE ICKS1 ICKS0 Initial value: 1 1 1 1 1 0 0 0 Read/Write:      R/W R/W R/W The STCR is an 8-bit readable/writable register that controls the serial communication interface and selects internal clock sources for the timer counters. The STCR is initialized to H'F8 at a reset. Bits 7 to 3Reserved: These bits cannot be modified and are always read as “1.
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8.3 Operation 8.3.1 TCNT Incrementation Timing The timer counter increments on a pulse generated once for each period of the selected (internal or external) clock source. Internal Clock: Internal clock sources are created from the system clock by a prescaler. The counter increments on an internal TCNT clock pulse generated from the falling edge of the prescaler output, as shown in figure 8.2. Bits CKS2 to CKS0 of the TCR and bits ICKS1 and ICKS0 of the STCR can select one of the six internal clocks.
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Ø External clock source TCNT clock pulse N N-1 TCNT N+1 Figure 8.3 Count Timing for External Clock Input 8.3.2 Compare Match Timing (1) Setting of Compare-Match Flags A and B (CMFA and CMFB): The compare-match flags are set to “1” by an internal compare-match signal generated when the timer count matches the time constant in TCNT or TCOR. The compare-match signal is generated at the last state in which the match is true, just before the timer counter increments to a new value.
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(2) Output Timing: When a compare-match event occurs, the timer output (TMO0 or TMO1) changes as specified by the output select bits (OS3 to OS0) in the TCSR. Depending on these bits, the output can remain the same, change to “0,” change to “1,” or toggle. Figure 8.5 shows the timing when the output is set to toggle on compare-match A. Ø Internal compare-match A signal Timer output (TMO) Figure 8.
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8.3.3 External Reset of TCNT When the CCLR1 and CCLR0 bits in the TCR are both set to “1,” the timer counter is cleared on the rising edge of an external reset input. Figure 8.7 shows the timing of this operation. The timer reset pulse width must be at least 1.5 system clock periods. Ø External reset input (TMRI) Internal clear pulse N-1 TCNT N N' 00 Figure 8.7 Timing of External Reset 8.3.
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8.4 Interrupts Each channel in the 8-bit timer can generate three types of interrupts: compare-match A and B (CMIA and CMIB), and overflow (OVI). Each interrupt is requested when the corresponding enable bits are set in the TCR and TCSR. Independent signals are sent to the interrupt controller for each interrupt. Table 8.3 lists information about these interrupts. Table 8.
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8.6 Application Notes Application programmers should note that the following types of contention can occur in the 8-bit timer. (1) Contention between TCNT Write and Clear: If an internal counter clear signal is generated during the T3 state of a write cycle to the timer counter, the clear signal takes priority and the write is not performed. Figure 8.10 shows this type of contention.
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(2) Contention between TCNT Write and Increment: If a timer counter increment pulse is generated during the T3 state of a write cycle to the timer counter, the write takes priority and the timer counter is not incremented. Figure 8.11 shows this type of contention. Write cycle: CPU writes to TCNT T1 T2 T3 Ø Internal Address bus TCNT address Internal write signal TCNT clock pulse TCNT N M Write data Figure 8.11 TCNT Write-Increment Contention Rev. 3.
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(3) Contention between TCOR Write and Compare-Match: If a compare-match occurs during the T3 state of a write cycle to TCORA or TCORB, the write takes precedence and the compare-match signal is inhibited. Figure 8.12 shows this type of contention. Write cycle: CPU writes to TCORA or TCORB T1 T2 T3 Ø Internal address bus TCOR address Internal write signal TCNT N TCORA or TCORB N N+1 M TCOR write data Compare-match A or B signal Inhibited Figure 8.
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(5) Incrementation Caused by Changing of Internal Clock Source: When an internal clock source is changed, the changeover may cause the timer counter to increment. This depends on the time at which the clock select bits (CKS1, CKS0) are rewritten, as shown in table 8.5. The pulse that increments the timer counter is generated at the falling edge of the internal clock source signal. If clock sources are changed when the old source is High and the new source is Low, as in case No. 3 in table 8.
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Table 8.5 Effect of Changing Internal Clock Sources (cont) No. Description Timing chart 3 High → Low* : Clock select bits are rewritten while old clock source is High and new clock source is Low. 1 Old clock source New clock source *2 TCNT clock pulse TCNT N N +1 N +2 CKS rewrite 4 High → High: Clock select bits are rewritten while both clock sources are High. Old clock source New clock source TCNT clock pulse TCNT N N +1 N+2 CKS rewrite Notes: 1.
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Section 9 PWM Timers 9.1 Overview The H8/338 Series has an on-chip pulse-width modulation (PWM) timer module with two independent channels (PWM0 and PWM1). Both channels are functionally identical. Each PWM channel generates a rectangular output pulse with a duty cycle of 0 to 100%. The duty cycle is specified in an 8-bit duty register (DTR). 9.1.
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9.1.2 Block Diagram Figure 9.1 shows a block diagram of one PWM timer channel. Compare-match DTR Comparator TCNT Bus interface Output control Module data bus Pulse TCR Internal clock sources Ø/2 Ø/8 Clock Clock select Ø/32 Ø/128 Ø/256 Ø/1024 Ø/2048 Ø/4096 Legend: DTR : Timer Control Register (8 bits) TCNT : Duty Register (8 bits) TCR : Times Counter (8 bits) Figure 9.1 Block Diagram of PWM Timer Rev. 3.
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9.1.3 Input and Output Pins Table 9.1 lists the output pins of the PWM timer module. There are no input pins. Table 9.1 Output Pins of PWM Timer Module Name Abbreviation I/O Function PWM0 output PW0 Output Pulse output from PWM timer channel 0. PWM1 output PW1 Output Pulse output from PWM timer channel 1. 9.1.4 Register Configuration The PWM timer module has three registers for each channel as listed in table 9.2. Table 9.
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9.2.2 Duty Register (DTR)H'FFA1 (PWM0), H'FFA5 (PWM1) Bit: 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W The duty registers (DTR) are 8-bit readable/writable registers that specify the duty cycle of the output pulse. Any duty cycle from 0 to 100% can be selected, with a resolution of 1/250. Writing 0 (H'00) in a DTR gives a 0% duty cycle; writing 125 (H'7D) gives a 50% duty cycle; writing 250 (H'FA) gives a 100% duty cycle.
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Bit 7Output Enable (OE): This bit enables the timer counter and the PWM output. Bit 7 OE Description 0 PWM output is disabled. TCNT is cleared to H'00 and stopped. 1 PWM output is enabled. TCNT runs. (Initial value) Bit 6Output Select (OS): This bit selects positive or negative logic for the PWM output.
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Table 9.3 PWM Timer Parameters for 10MHz System Clock Internal Clock Frequency Resolution PWM Period PWM Frequency φ/2 200ns 50µs 20kHz φ/8 800ns 200µs 5kHz φ/32 3.2µs 800µs 1.25kHz φ/128 12.8µs 3.2ms 312.5Hz φ/256 25.6µs 6.4ms 156.3Hz φ/1024 102.4µs 25.6ms 39.1Hz φ/2048 204.8µs 51.2ms 19.5Hz φ/4096 409.6µs 102.4ms 9.8Hz 9.3 Operation 9.3.1 Timer Incrementation The PWM clock source is created from the system clock (φ) by a prescaler.
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9.3.2 PWM Operation Figure 9.3 is a timing chart of the PWM operation. Ø TCNT clock pulses OE N–1 (a) H' 00 TCNT (b) H' 01 H' 02 N+1 N H' F9 (d) H' 00 H' 01 (C) DTR N H' FF N written in DTR (a) (d) M M written in DTR (b) (C) ( OS = “0” ) PWM output ( OS = “1” ) (e) PWM 1 cycle Note: * Used for port 4 input/output: state depends on values in data register and data direction register. Figure 9.3 PWM Timing (1) Positive Logic (OS = “0”) ① When (OE = “0”) − (a) in Figure 9.
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iii) If the DTR value is changed (by writing the data “M” in figure 9.3), the new value becomes valid after the timer count changes from H'F9 to H'00. [(d) in figure 9.3] (2) Negative Logic (OS = “1”) - (e) in Figure 9.3: The operation is the same except that High and Low are reversed in the PWM output. [(e) in figure 9.3] 9.4 Application Notes Some notes on the use of the PWM timer module are given below.
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Section 10 Serial Communication Interface 10.1 Overview The H8/338 Series includes two serial communication interface channels (SCI0 and SCI1) for transferring serial data to and from other chips. Either synchronous or asynchronous communication can be selected. 10.1.
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TDR-empty, TSR-empty, receive-end, and receive-error interrupts are requested independently. 10.1.2 Block Diagram Bus interface Figure 10.1 shows a block diagram of one serial communication interface channel.
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Table 10.1 SCI Input/Output Pins Channel Name Abbr. I/O Function 0 Serial clock SCK0 Input/output Serial clock input and output. Receive data RxD0 Input Receive data input. Transmit data TxD0 Output Transmit data output. Serial clock SCK1 Input/output Serial clock input and output. Receive data RxD1 Input Receive data input. Transmit data TxD1 Output Transmit data output. 1 10.1.4 Register Configuration Table 10.2 lists the SCI registers.
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10.2 Register Descriptions 10.2.1 Receive Shift Register (RSR) Bit: 7 6 5 4 3 2 1 0 Read/Write:         The RSR is a shift register that converts incoming serial data to parallel data. When one data character has been received, it is transferred to the receive data register (RDR). The CPU cannot read or write the RSR directly. 10.2.
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10.2.4 Transmit Data Register (TDR)H'FFDB, H'FF8B Bit: 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W The TDR is an 8-bit readable/writable register that holds the next character to be transmitted. When the TSR becomes empty, the character written in the TDR is transferred to the TSR. Continuous data transmission is possible by writing the next byte in the TDR while the current byte is being transmitted from the TSR.
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Bit 6Character Length (CHR): This bit selects the character length in asynchronous mode. It is ignored in synchronous mode. Bit 6 CHR Description 0 8 bits per character. 1 7 bits per character. (Bits 0 to 6 of TDR and RDR are used for transmitting and receiving, respectively.) (Initial value) Bit 5Parity Enable (PE): This bit selects whether to add a parity bit in asynchronous mode. It is ignored in synchronous mode, and when a multiprocessor format is used.
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Bit 3Stop Bit Length (STOP): This bit selects the number of stop bits. It is ignored in the synchronous mode. Bit 3 STOP Description 0 One stop bit. Transmit: One stop bit is added. Receive: One stop bit is checked to detect framing errors. (Initial value) 1 Two stop bits. Transmit: Two stop bits are added. Receive: The first stop bit is checked to detect framing errors. If the second stop bit is a space (0), it is regarded as the next start bit.
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10.2.6 Serial Control Register (SCR)H'FFDA, H'FF8A Bit: 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value: 0 0 0 0 0 0 0 0 Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W The SCR is an 8-bit readable/writable register that enables or disables various SCI functions. It is initialized to H'00 at a reset and in the standby modes.
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Bit 4Receive Enable (RE): This bit enables or disables the receive function. When the receive function is enabled, the RxD pin is automatically used for input. When the receive function is disabled, the RxD pin is available as a general-purpose I/O port. Bit 4 RE Description 0 The receive function is disabled. The RxD pin can be used for general-purpose I/O. (Initial value) 1 The receive function is enabled. The RxD pin is used for input.
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Bit 2Transmit-End Interrupt Enable (TEIE): This bit enables or disables the TSR-empty interrupt (TEI) requested when the transmit-end bit (TEND) in the serial status register (SSR) is set to “1.” Bit 2 TEIE Description 0 The TSR-empty interrupt request (TEI) is disabled. 1 The TSR-empty interrupt request (TEI) is enabled. (Initial value) Bit 1Clock Enable 1 (CKE1): This bit selects the internal or external clock source for the baud rate generator.
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10.2.7 Serial Status Register (SSR)H'FFDC, H'FF8C Bit: 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT Initial value: 1 0 0 0 0 1 0 0 Read/Write: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Note: Software can write a “0” to clear the flags, but cannot write a “1” in these bits. The SSR is an 8-bit register that indicates transmit and receive status. It is initialized to H'84 at a reset and in the standby modes.
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Bit 4Framing Error (FER): This bit indicates a framing error during data reception in asynchronous mode. It has no meaning in synchronous mode. Bit 4 FER Description 0 To clear FER, the CPU must read FER after it has been set to “1,” then write a “0” in this bit. 1 This bit is set to “1” if a framing error occurs (stop bit = “0”).
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Bit 1Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in data received in a multiprocessor format in asynchronous communication mode. This bit is cleared to “0” in synchronous mode, or when a multiprocessor format is not used. If the RE bit is cleared to “0” when a multiprocessor format is used, the MPB bit retains its previous value. MPB can be read but not written. Bit 1 MPB Description 0 Multiprocessor bit = “0” in receive data. 1 Multiprocessor bit = “1” in receive data.
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10.2.8 Bit Rate Register (BRR)H'FFD9, H'FF89 Bit: 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W The BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in the SMR, determines the baud rate output by the baud rate generator. The BRR is initialized to H'FF (the slowest rate) at a reset and in the standby modes. Tables 10.3 and 10.4 show examples of BRR (N) and CKS (n) settings for commonly used bit rates. Table 10.
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Table 10.3 Examples of BRR Settings in Asynchronous Mode (2) XTAL Frequency (MHz) 4.9152 6 7.3728 8 Bit Rate n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 1 174 −0.26 2 52 +0.50 2 64 +0.70 2 70 +0.03 150 1 127 0 1 155 +0.16 1 191 0 1 207 +0.16 300 0 255 0 1 77 +0.16 1 95 0 1 103 +0.16 600 0 127 0 0 155 +0.16 0 191 0 0 207 +0.16 1200 0 63 0 0 77 +0.16 0 95 0 0 103 +0.16 2400 0 31 0 0 38 +0.16 0 47 0 0 51 +0.
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Table 10.3 Examples of BRR Settings in Asynchronous Mode (4) XTAL Frequency (MHz) 14.7456 16 19.6608 20 Bit Rate n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 130 −0.07 2 141 +0.03 2 174 −0.26 2 177 −0.25 150 2 95 0 2 103 +0.16 2 127 0 2 129 +0.16 300 1 191 0 1 207 +0.16 1 255 0 2 64 +0.16 600 1 95 0 1 103 +0.16 1 127 0 1 129 +0.16 1200 0 191 0 0 207 +0.16 0 255 0 1 64 +0.16 2400 0 95 0 0 103 +0.
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Table 10.4 Examples of BRR Settings in Synchronous Mode XTAL Frequency (MHz) 2 4 8 10 16 20 Bit Rate n N n N n N n N n N n N 100             250 1 249 2 124 2 249   3 124   500 1 124 1 249 2 124   2 249   1k 0 249 1 124 1 249   2 124   2.
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10.2.9 Serial/Timer Control Register (STCR)H'FFC3 Bit: 7 6 5 4 3 2 1 0      MPE ICKS1 ICKS0 Initial value: 1 1 1 1 1 0 0 0 Read/Write:      R/W R/W R/W The STCR is an 8-bit readable/writable register that controls the operating mode of the serial communication interface and selects input clock sources for the 8-bit timer counters (TCNT). The STCR is initialized to H'F8 by a reset. Bits 7 to 3Reserved: These bits cannot be modified and are always read as “1.
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10.3 Operation 10.3.1 Overview The SCI supports serial data transfer in two modes. In asynchronous mode each character is synchronized individually. In synchronous mode communication is synchronized with a clock signal. The selection of asynchronous or synchronous mode and the communication format depend on settings in the SMR as indicated in table 10.5. The clock source depends on the settings of the C/A bit in the SMR and the CKE1 and CKE0 bits in the SCR as indicated in table 10.6.
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Table 10.
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10.3.2 Asynchronous Mode In asynchronous mode, each transmitted or received character is individually synchronized by framing it with a start bit and stop bit. Full duplex data transfer is possible because the SCI has independent transmit and receive sections. Double buffering in both sections enables the SCI to be programmed for continuous data transfer. Figure 10.2 shows the general format of one character sent or received in asynchronous mode.
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Table 10.
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(3) Transmitting and Receiving Data • SCI Initialization: Before transmitting or receiving, software must clear the TE and RE bits to “0” in the serial control register (SCR), then initialize the SCI as follows. Note: When changing the communication mode or format, always clear the TE and RE bits to “0” before following the procedure given below. Clearing TE to “0” sets TDRE to “1” and initializes the transmit shift register (TSR).
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• Transmitting Serial Data: Follow the procedure below for transmitting serial data. 1 Initialize Start transmitting 2 1. SCI initialization: the transmit data output function of the TxD pin is selected automatically. 2. SCI status check and transmit data write: read the serial status register (SSR), check that the TDRE bit is "1," then write transmit data in the transmit data register (TDR) and clear TDRE to "0.
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In transmitting serial data, the SCI operates as follows. 1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to “0” the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from TDR into the transmit shift register (TSR). 2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to “1” and starts transmitting. If the TIE bit (TDR-empty interrupt enable) is set to “1” in SCR, the SCI requests a TXI interrupt (TDR-empty interrupt) at this time.
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• Receiving Serial Data: Follow the procedure below for receiving serial data. 1 Initialize 1. SCI initialization: the receive data function of the RxD pin is selected automatically. 2. SCI status check and receive data read: read the serial status register (SSR), check that RDRF is set to "1," then read receive data from the receive data register (RDR) and clear RDRF to "0." Transition of the RDRF bit from "0" to "1" can be reported by an RXI interrupt. 3.
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In receiving, the SCI operates as follows. 1. The SCI monitors the receive data line and synchronizes internally when it detects a start bit. 2. Receive data are shifted into RSR in order from LSB to MSB. 3. The parity bit and stop bit are received. After receiving these bits, the SCI makes the following checks: (a) Parity check: the number of 1s in the receive data must match the even or odd parity setting of the O/E bit in SMR. (b) Stop bit check: the stop bit value must be “1.
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"1" Start bit "0" Parity bit Data D0 D1 D7 0/1 Stop bit "1" Start bit "0" Parity bit Data D0 D1 D7 0/1 Stop bit "0" "1" Mark (idle) state RDRF FER RXI request 1 frame RXI interrupt handler reads data in RDR and clears RDRF to "0" Framing error, ERI request Figure 10.8 Example of SCI Receive Operation (8-bit data with parity and one stop bit) (4) Multiprocessor Communication The multiprocessor communication function enables several processors to share a single serial communication line.
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Transmitting processor Serial communication line Serial data Receiving processor A Receiving processor B Receiving processor C Receiving processor D (ID = 01) (ID = 02) (ID = 03) (ID = 04) H'01 (MPB = 1) ID-sending cycle: receiving processor address H'AA (MPB = 0) Data-sending cycle: data sent to receiving processor specified by ID MPB: multiprocessor bit Figure 10.
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1 Initialize 1. SCI initialization: the receive data function of the RxD pin is selected automatically. Start receiving 2. ID receive cycle: Set the MPIE bit in the serial control register (SCR) to "1." 2 Set MPIE bit to "1" in SCR 3. 3 Read RDRF bit in SSR SCI status check and ID check: read the serial status register (SSR), check that RDRF is set to "1," then read receive data from the receive data register (RDR) and compare with the processor's own ID.
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Figure 10.11 shows an example of SCI receive operation using a multiprocessor format.
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10.3.3 Synchronous Mode (1) Overview: In clocked synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver share the same clock but are otherwise independent, so full duplex communication is possible. The transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress.
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(2) Transmitting and Receiving Data • SCI Initialization: The SCI must be initialized in the same way as in asynchronous mode. See figure 10.4. When switching from asynchronous mode to clocked synchronous mode, check that the ORER, FER, and PER bits are cleared to “0.” Transmitting and receiving cannot begin if ORER, FER, or PER is set to “1.” • Transmitting Serial Data: Follow the procedure below for transmitting serial data.
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2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to “1” and starts transmitting. If the TIE bit (TDR-empty interrupt enable) in SCR is set to “1,” the SCI requests a TXI interrupt (TDR-empty interrupt) at this time. If clock output is selected the SCI outputs eight serial clock pulses, triggered by the clearing of the TDRE bit to “0.” If an external clock source is selected, the SCI outputs data in synchronization with the input clock.
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1 2 Initialize 1. SCI initialization: the receive data function of the RxD pin is selected automatically. Start receiving 2. SCI status check and receive data read: read the serial status register (SSR), check that RDRF is set to "1," then read receive data from the receive data register (RDR) and clear RDRF to "0." Transition of the RDRF bit from "0" to "1" can be reported by an RXI interrupt. 3.
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After receiving the data, the SCI checks that RDRF is “0” so that receive data can be loaded from RSR into RDR. If this check passes, the SCI sets RDRF to “1” and stores the received data in RDR. If the check does not pass (receive error), the SCI operates as indicated in table 10.8. Note: Both transmitting and receiving are disabled while a receive error flag is set. The RDRF bit is not set to “1.” Be sure to clear the error flag. 3.
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Initialize 1 1. SCI initialization: the transmit data output function of the TxD pin and receive data input function of the RxD pin are selected, enabling simultaneous transmitting and receiving. 2. SCI status check and transmit data write: read the serial status register (SSR), check that the TDRE bit is "1," then write transmit data in the transmit data register (TDR) and clear TDRE to "0." Transition of the TDRE bit from "0" to "1" can be reported by a TXI interrupt. 3.
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10.4 Interrupts The SCI can request four types of interrupts: ERI, RxI, TxI, and TEI. Table 10.9 indicates the source and priority of these interrupts. The interrupt sources can be enabled or disabled by the TIE, RIE, and TEIE bits in the SCR. Independent signals are sent to the interrupt controller for each interrupt source, except that the receive-error interrupt (ERI) is the logical OR of three sources: overrun error, framing error, and parity error.
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Table 10.10 SSR Bit States and Data Transfer when Multiple Receive Errors Occur SSR Bits Receive Error RDRF Overrun error 1* Framing error 0 Parity error 0 1 ORER FER PER RSR → 2 RDR* 1 0 0 No 0 1 0 Yes 0 0 1 Yes 1* 1 1 1 0 No Overrun and parity errors 1* 1 1 0 1 No Framing and parity errors 0 0 1 1 Yes 1 1 1 No Overrun and framing errors Overrun, framing, and parity errors 1* 1 Notes: 1. Set to “1” before the overrun error occurs. 2.
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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 Basic clock –7.5 pulses Receive data +7.5 pulses Start bit D0 D1 Sync sampling Data sampling Figure 10.18 Sampling Timing (Asynchronous mode) M = {(0.5 − 1/2N) − (D − 0.5)/N - (L − 0.5) F} × 100 [%] (1) M: Receive margin N: Ratio of basic clock to baud rate (N=16) D: Duty factor of clock-ratio of High pulse width to Low width (0.5 to 1.
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Section 11 A/D Converter 11.1 Overview The H8/338 Series includes an analog-to-digital converter module with eight input channels. A/D conversion is performed by the successive approximations method with 8-bit resolution. 11.1.1 Features The features of the on-chip A/D module are: • 8-bit resolution • Eight analog input channels • Rapid conversion Conversion time is 12.2µs per channel (minimum) with a 10MHz system clock • Single and scan modes  Single mode: A/D conversion is performed once.
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Block Diagram Bus interface 11.1.
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11.1.3 Input Pins Table 11.1 lists the input pins used by the A/D converter module. The eight analog input pins are divided into two groups, consisting of analog inputs 0 to 3 (AN 0 to AN3) and analog inputs 4 to 7 (AN4 to AN7), respectively. Table 11.1 A/D Input Pins Name Abbreviation I/O Function Analog supply voltage AVCC Input Power supply and reference voltage for the analog circuits. Analog ground AVSS Input Ground and reference voltage for the analog circuits.
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11.2 Register Descriptions 11.2.1 A/D Data Registers (ADDR)H'FFE0 to H'FFE6 Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 Read/Write: R R R R R R R ADDRn: R (n = A to D) The four A/D data registers (ADDRA to ADDRD) are 8-bit read-only registers that store the results of A/D conversion. Each data register is assigned to two analog input channels as indicated in table 11.3. The A/D data registers are always readable by the CPU.
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Bit 7A/D End Flag (ADF): This status flag indicates the end of one cycle of A/D conversion. Bit 7 ADF Description 0 To clear ADF, the CPU must read ADF after it has been set to “1,” then write a “0” in this bit. 1 This bit is set to 1 at the following times: (Initial value) (1) Single mode: when one A/D conversion is completed. (2) Scan mode: when inputs on all selected channels have been converted.
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Bit 3Clock Select (CKS): This bit controls the A/D conversion time. The conversion time should be changed only when the ADST bit is cleared to “0.” Bit 3 CKS Description 0 Conversion time = 242 states (max) 1 Conversion time = 122 states (max) (Initial value) Bits 2 to 0Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit combine to select one or more analog input channels. The channel selection should be changed only when the ADST bit is cleared to “0.
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11.2.3 A/D Control Register (ADCR)H'FFEA Bit: 7 6 5 4 3 2 1 0 TRGE       CHS Initial value: 0 1 1 1 1 1 1 0 Read/Write: R/W       R/W The A/D control register (ADCR) is an 8-bit readable/writable register that enables or disables the A/D external trigger signal. The ADCR is initialized to H'7E at a reset and in the standby modes. Bit 7Trigger Enable (TRGE): This bit enables the ADTRG (A/D external trigger) signal to set the ADST bit and start A/D conversion.
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11.3 Operation The A/D converter performs 8 successive approximations to obtain a result ranging from H'00 (corresponding to AVSS) to H'FF (corresponding to AVCC). The A/D converter module can be programmed to operate in single mode or scan mode as explained below. 11.3.1 Single Mode (SCAN = 0) The single mode is suitable for obtaining a single data value from a single channel.
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Value set in ADCSR ADF ADIE ADST SCAN CKS CH2 CH1 CH0 0 1 1 0 0 0 0 1 (2) The A/D converter converts the voltage level at the AN1 input pin to a digital value. At the end of the conversion process the A/D converter transfers the result to register ADDRB, sets the ADF bit to “1,” clears the ADST bit to “0,” and halts. (3) ADF = “1” and ADIE = “1,” so an A/D interrupt is requested. (4) The user-coded A/D interrupt-handling routine is started.
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Interrupt (ADI) Set* ADIE A/D conversion starts Set* Set* ADST Clear* Clear* ADF Channel 0 (AN0) Waiting Channel 1 (AN1) Waiting Channel 2 (AN2) Waiting Channel 3 (AN3) Waiting A/D conversion (1) Waiting A/D conversion (2) Waiting ADDRA Read result ADDRB A/D conversion result (1) Read result A/D conversion result (2) ADDRC ADDRD Note: * indicates execution of a software instruction Figure 11.2 A/D Operation in Single Mode (when Channel 1 is Selected) Rev. 3.
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11.3.2 Scan Mode (SCAN = 1) The scan mode can be used to monitor analog inputs on one or more channels. When the ADST bit is set to “1,” either by software or by a High-to-Low transition of the ADTRG signal (if enabled), A/D conversion starts from the first channel selected by the CH bits. When CH2 = “0” the first channel is AN0. When CH2 = “1” the first channel is AN4. If the scan group includes more than one channel (i.e.
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(4) After all selected channels (AN0 to AN2) have been converted, the AD converter sets the ADF bit to “1.” If the ADIE bit is set to “1,” an A/D interrupt (ADI) is requested. Then the A/D converter begins converting AN0 again. (5) Steps (2) to (4) are repeated cyclically as long as the ADST bit remains set to “1.” To stop the A/D converter, software must clear the ADST bit to “0.
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11.3.3 Input Sampling Time and A/D Conversion Time The A/D converter includes a built-in sample-and-hold circuit. Sampling of the input starts at a time tD after the ADST bit is set to “1.” The sampling process lasts for a time tSPL. The actual A/D conversion begins after sampling is completed. Figure 11.4 shows the timing of these steps. Table 11.4 (a) lists the conversion times for the single mode. Table 11.4 (b) lists the conversion times for the scan mode.
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(1) Ø Internal address bus (2) Write signal Input sampling timing ADF tD tSPL tCONV Legend: (1) : ADCSR write cycle (2) : ADCSR address tD : Synchronization delay : Input sampling time tSPL tCONV : Total A/D conversion time Figure 11.4 A/D Conversion Timing Table 11.
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Table 11.4 (b) A/D Conversion Time (Scan mode) CKS = “0” CKS = “1” Item Symbol Min Typ Max Min Typ Max Synchronization delay tD 18  33 10  17 Input sampling time tSPL  63   31  Total A/D conversion time tCONV 259  274 131  138 Note: Values in the tables above are numbers of states. 11.3.4 External Trigger Input Timing A/D conversion can be started by external trigger input at the ADTRG pin.
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11.4 Interrupts The A/D conversion module generates an A/D-end interrupt request (ADI) at the end of A/D conversion. The ADI interrupt request can be enabled or disabled by the ADIE bit in the A/D control/status register (ADCSR). Rev. 3.
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Section 12 D/A Converter 12.1 Overview The H8/338 Series has an on-chip D/A converter module with two channels. 12.1.1 Features Features of the D/A converter module are listed below. • Eight-bit resolution • Two-channel output • Maximum conversion time: 10µs (with 30pF load capacitance) • Output voltage: 0V to AVCC Rev. 3.
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12.1.2 Block Diagram Bus interface Figure 12.1 shows a block diagram of the D/A converter. Module data bus DACR 8 Bit D/A DADR0 DA0 DADR1 AVCC DA1 AVSS Control circuit Legend: DACR : D/A control register DADR0 : D/A data register 0 DADR1 : D/A data register 1 Figure 12.1 D/A Converter Block Diagram Rev. 3.
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12.1.3 Input and Output Pins Table 12.1 lists the input and output pins used by the D/A converter module. Table 12.1 Input and Output Pins of D/A Converter Module Name Abbreviation I/O Function Analog supply voltage AVCC Input Power supply and reference voltage for analog circuits Analog ground AVSS Input Ground and reference voltage for analog circuits Analog output 0 DA0 Output Analog output channel 0 Analog output 1 DA1 Output Analog output channel 1 12.1.
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12.2 Register Descriptions 12.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) H'FFA8, H'FFA9 Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W D/A data registers 0 and 1 (DADR0 and DADR1) are 8-bit readable and writable registers that store data to be converted. When analog output is enabled, the value in the D/A data register is converted and output continuously at the analog output pin.
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Bit 6D/A Output Enable 0 (DAOE0): Controls analog output from the D/A converter. Bit 6 DAOE0 Description 0 Analog output at DA0 is disabled. 1 D/A conversion is enabled on channel 0. Analog output is enabled at DA0. Bit 5D/A Enable (DAE): Controls analog output from the D/A converter, in combination with bits DAOE0 and DAOE1. D/A conversion is controlled independently on channels 0 and 1 when DAE = 0. Channels 0 and 1 are controlled together when DAE = 1.
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12.3 Operation The D/A converter module has two built-in D/A converter circuits that can operate independently. D/A conversion is performed continuously whenever enabled by the D/A control register. When a new value is written in DADR0 or DADR1, conversion of the new value begins immediately. The converted result is output by setting the DAOE0 or DAOE1 bit to “1.” An example of conversion on channel 0 is given next. Figure 12.2 shows the timing. (1) Software writes the data to be converted in DADR0.
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Section 13 RAM 13.1 Overview The H8/338 includes 2k bytes of on-chip static RAM. The H8/337 and H8/336 have 1k byte. The RAM is connected to the CPU by a 16-bit data bus. Both byte and word access to the on-chip RAM are performed in two states, enabling rapid data transfer and instruction execution. The on-chip RAM is assigned to addresses H'F780 to H'FF7F in the address space of the H8/338, and addresses H'FB80 to H'FF7F in the address space of the H8/337 and H8/336.
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13.3 RAM Enable Bit (RAME) in System Control Register (SYSCR) The on-chip RAM is enabled or disabled by the RAME (RAM Enable) bit in the system control register (SYSCR). Bit: 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0  NMIEG DPME RAME Initial value: 0 0 0 0 1 0 0 1 Read/Write: R/W R/W R/W R/W  R/W R/W R/W The only bit in the system control register that concerns the on-chip RAM is the RAME bit. See section 2.2, "System Control Register," for the other bits.
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Section 14 ROM 14.1 Overview The H8/338 includes 48k bytes of high-speed, on-chip ROM. The H8/337 has 32k bytes. The H8/336 has 24k bytes. The on-chip ROM is connected to the CPU via a 16-bit data bus. Both byte data and word data are accessed in two states, enabling rapid data transfer and instruction fetching. The on-chip ROM is enabled or disabled depending on the MCU operating mode, which is determined by the inputs at the mode pins (MD1 and MD0). See table 14.1. Table 14.
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14.1.1 Block Diagram Figure 14.1 is a block diagram of the on-chip ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'0000 H'0001 H'0002 H'0003 On-chip ROM H'BFFE H'BFFF Even addresses Odd addresses Figure 14.1 Block Diagram of On-Chip ROM (H8/338) 14.2 PROM Mode (H8/338, H8/337) 14.2.1 PROM Mode Setup In the PROM mode of the PROM version of the H8/338 and H8/337, the usual microcomputer functions are halted to allow the on-chip PROM to be programmed.
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14.2.2 Socket Adapter Pin Assignments and Memory Map The H8/338 and H8/337 can be programmed with a general-purpose PROM writer by using a socket adapter to change the pin-out to 32 pins. There are different socket adapters for different packages as listed in table 14.3. The same socket adapters can be used for both the H8/338 and H8/337. Figure 14.2 shows the socket adapter pin assignments. Table 14.
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H8/337, H8/338 FP-80A 1 CG-84, CP-84 EPROM Socket Pin Pin HN27C101 (32 pins) 12 RES V PP 1 6 17 NMI EA 9 26 65 79 P3 0 EO 0 13 66 80 P3 1 EO 1 14 67 81 P3 2 EO 2 15 68 82 P3 3 EO 3 17 69 83 P3 4 EO 4 18 70 84 P3 5 EO 5 19 71 1 P3 6 EO 6 20 72 3 P3 7 EO 7 21 64 78 P1 0 EA 0 12 63 77 P1 1 EA 1 11 62 76 P1 2 EA 2 10 61 75 P1 3 EA 3 9 60 74 P1 4 EA 4 8 59 73 P1 5 EA 5 7 58 72 P1 6 EA 6 6 57 71 P1 7 EA 7 5 55 69 P2 0
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Address in MCU mode Address in PROM mode H'0000 H'0000 On-chip PROM H'BFFF H'BFFF Undetermined output* H'1FFFF Note: * If this address area is read in PROM mode, the output data are undetermined. Figure 14.3 H8/338 Memory Map in PROM Mode Rev. 3.
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Address in MCU mode Address in PROM mode H'0000 H'0000 On-chip PROM H'7FFF H'7FFF Undetermined output* H'1FFFF Note: * If this address area is read in PROM mode, the output data are undetermined. Figure 14.4 H8/337 Memory Map in PROM Mode Rev. 3.
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14.3 Programming The write, verify, and other sub-modes of the PROM mode are selected as shown in table 14.4. Table 14.
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START Set program/verify mode VCC = 6.0V ±0.25V, VPP = 12.5V ±0.3V Address = 0 n=1 n+1 n Yes No n < 25? Program tPW = 0.2 ms ±5% No Address + 1 Verify OK? Yes Program tOPW = 0.2n ms Last address? No Yes Set read mode VCC = 5.0V ±0.25V, VPP = VCC Error NoGo All addresses read? Go END Figure 14.5 High-Speed Programming Flowchart Rev. 3.
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Table 14.5 DC Characteristics (when VCC = 6.0V ±0.25V, VPP = 12.5V ±0.3V, VSS = 0V, Ta = 25°C ±5°C) Item Symbol Min Typ Max Unit Measurement Conditions Input High voltage EO7 − EO0, A16 − A0, OE, CE, PGM VIH 2.4  VCC + 0.3 V Input Low voltage EO7 − EO0, A16 − A0, OE, CE, PGM VIL −0.3  0.8 V Output High voltage EO7 − EO0 VOH 2.4   V IOH = −200µA Output Low voltage EO7 − EO0 VOL   0.45 V IOL = 1.
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Table 14.6. AC Characteristics (cont) (when VCC = 6.0V ±0.25V, VPP = 12.5V ±0.3V, Ta = 25°C ±5°C) Item Symbol Min Typ Max Unit Measurement Conditions OE pulse width for overwriteprogramming tOPW 0.19  5.25 ms See figure 14.6* VCC setup time tVCS 2   µs CE setup time tCES 2   µs Data output delay time tOE 0  150 ns Note: Input pulse level: 0.8V to 2.2V Input rise/fall time ≤ 20ns Timing reference levels: input1.0V, 2.0V; output0.8V, 2.
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14.3.2 Notes on Writing (1) Write with the specified voltages and timing. The programming voltage (VPP) is 12.5V. Caution: Applied voltages in excess of the specified values can permanently destroy the chip. Be particularly careful about the PROM writer’s overshoot characteristics. If the PROM writer is set to HN27C101 specifications, VPP will be 12.5V. (2) Before writing data, check that the socket adapter and chip are correctly mounted in the PROM writer.
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14.3.3 Reliability of Written Data An effective way to assure the data holding characteristics of the programmed chips is to bake them at 150°C, then screen them for data errors. This procedure quickly eliminates chips with PROM memory cells prone to early failure. Figure 14.7 shows the recommended screening procedure. Write and verify program Bake with power off 150C+10C, 48Hr + 8Hr* – 0Hr Read and check program VCC= 5.
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14.3.4 Erasing of Data The windowed package enables data to be erased by illuminating the window with ultraviolet light. Table 14.7 lists the erasing conditions. Table 14.7 Erasing Conditions Item Value Ultraviolet wavelength 253.7 nm Minimum illumination 15W⋅s/cm 2 2 The conditions in table 14.7 can be satisfied by placing a 12000µW/cm ultraviolet lamp 2 or 3 centimeters directly above the chip and leaving it on for about 20 minutes. 14.
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(3) Note on 84-Pin LCC Package: A socket should always be used when the 84-pin LCC package is mounted on a printed-circuit board. Table 14.8 lists the recommended socket. Table 14.8 Recommended Socket for Mounting 84-Pin LCC Package Manufacturer Code Sumitomo 3-M 284-1273-00-1102J Rev. 3.
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Section 15 Power-Down State 15.1 Overview The H8/338 Series has a power-down state that greatly reduces power consumption by stopping some or all of the chip functions. The power-down state includes three modes: (1) Sleep mode − a software-triggered mode in which the CPU halts but the rest of the chip remains active (2) Software standby mode − a software-triggered mode in which the entire chip is inactive (3) Hardware standby mode − a hardware-triggered mode in which the entire chip is inactive Table 15.
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15.2 System Control Register: Power-Down Control Bits Bits 7 to 4 of the system control register (SYSCR) concern the power-down state. Specifically, they concern the software standby mode. Table 15.2 lists the attributes of the system control register. Table 15.
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When the on-chip clock pulse generator is used, the STS bits should be set to allow a settling time of at least 10ms. Table 15.3 lists the settling times selected by these bits at several clock frequencies and indicates the recommended settings. When the chip is externally clocked, the STS bits can be set to any value. The minimum value (STS2 = STS1 = STS0 = “0”) is recommended. Table 15.3 Times Set by Standby Timer Select Bits (Unit: ms) STS2 STS1 STS0 Settling Time (states) 0 0 0 8192 0.8 1.
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15.3 Sleep Mode The sleep mode provides an effective way to conserve power while the CPU is waiting for an external interrupt or an interrupt from an on-chip supporting module. 15.3.1 Transition to Sleep Mode When the SSBY bit in the system control register is cleared to “0,” execution of the SLEEP instruction causes a transition from the program execution state to the sleep mode. After executing the SLEEP instruction, the CPU halts, but the contents of its internal registers remain unchanged.
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15.4 Software Standby Mode In the software standby mode, the system clock stops and chip functions halt, including both CPU functions and the functions of the on-chip supporting modules. Power consumption is reduced to an extremely low level. The on-chip supporting modules and their registers are reset to their initial states, but as long as a minimum necessary voltage supply is maintained (at least 2V), the contents of the CPU registers and on-chip RAM remain unchanged. 15.4.
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15.4.3 Sample Application of Software Standby Mode In this example the chip enters the software standby mode when NMI goes Low and exits when NMI goes High, as shown in figure 15.1. The NMI edge bit (NMIEG) in the system control register is originally cleared to “0,” selecting the falling edge. When NMI goes Low, the NMI interrupt handling routine sets NMIEG to “1,” sets SSBY to “1” (selecting the rising edge), then executes the SLEEP instruction. The chip enters the software standby mode.
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15.4.4 Application Note 1. The I/O ports retain their current states in the software standby mode. If a port is in the High output state, the current dissipation caused by the High output current is not reduced. 2. When software standby mode is entered under condition (a) or (b) below, current dissipation is higher (ICC = 100 to 300 µA) than normal in standby mode.
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15.5 Hardware Standby Mode 15.5.1 Transition to Hardware Standby Mode Regardless of its current state, the chip enters the hardware standby mode whenever the STBY pin goes Low. The hardware standby mode reduces power consumption drastically by halting the CPU, stopping all the functions of the on-chip supporting modules, and placing I/O ports in the high-impedance state. The registers of the on-chip supporting modules are reset to their initial values.
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Clock pulse generator RES STBY Clock settling time Restart Figure 15.2 Hardware Standby Mode Timing Rev. 3.
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Section 16 Electrical Specifications 16.1 Absolute Maximum Ratings Table 16.1 lists the absolute maximum ratings. Table 16.1 Absolute Maximum Ratings Item Symbol Rating Unit Supply voltage VCC −0.3 to +7.0 V Programming voltage VPP −0.3 to +13.5 V Ports 1 − 6, 8, 9 Vin −0.3 to VCC + 0.3 V Port 7 Vin −0.3 to AVCC + 0.3 V Analog supply voltage AVCC −0.3 to +7.0 V Analog input voltage VAN −0.3 to AVCC + 0.
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Table 16.2 DC Characteristics (5V version) Conditions: VCC = 5.0V ±10%, AVCC = 5.0V ±10%*, VSS = AVSS = 0V, Ta = −20 to 75°C (regular specifications), Ta = −40 to 85°C (wide-range specifications) Item Schmitt trigger input voltage (1) P67 − P62, P60, P86 − P80, P97, P94 − P90 Symbol Min Typ Max Measurement Unit Conditions VT− + VT + VT −VT− 1.0   V   VCC × 0.7 V Input High voltage RES, STBY, NMI VIH MD1, MD0 (2) EXTAL P77 − P70 0.4   V VCC − 0.7  VCC + 0.3 V 2.0  AVCC + 0.
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Table 16.2 DC Characteristics (5V version) (cont) Conditions: VCC = AVCC = 5.
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Table 16.3 DC Characteristics (3V version) Conditions: VCC = 3.0V ±10%, AVCC = 5.0V ±10%* , VSS = AVSS = 0V, Ta = −20 to 70°C 1 Item Schmitt trigger 2 input voltage* (1) Input High voltage*2 (2) Symbol Min P67 − P62, P60, P86 − P80, P97, P94 − P90 VT− RES, STBY Measurement Unit Conditions VCC × 0.15   V   VCC × 0.7 V VT − VT 0.2   V VIH VCC × 0.9  VCC + 0.3 V P77 − P70 VCC × 0.7  AVCC + 0.3 V Input pins other than (1) and (2) above VCC × 0.7  VCC + 0.3 V −0.
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Table 16.3 DC Characteristics (3V version) (cont) Conditions: VCC = 3.0V ±10%, AVCC = 5.0V ±10%* , VSS = AVSS = 0V, Ta = −20 to 70°C 1 Typ Max Unit Measurement Conditions   60 pF Vin = 0V NMI   30 pF f = 1MHz All input pins except RES and NMI   15 pF Ta = 25°C Normal operation ICC  6  mA f = 3MHz Sleep mode  10 20 mA f = 5MHz  4  mA f = 3MHz  6 12 mA f = 5MHz  0.01 5.0 µA  2.0 5.0 mA  0.01 5.0 µA 2.
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Table 16.4 Allowable Output Current Values (5V version) Conditions: VCC = AVCC = 5.0V ±10%, VSS = AVSS = 0V, Ta = −20 to 75°C (regular specifications), Ta = −40 to 85°C (wide-range specifications) Item Allowable output Low current (per pin) Symbol Min Ports 1 and 2 IOL Other output pins Allowable output Low current (total) Ports 1 and 2, total ΣIOL Total of all output Typ Max Unit   10 mA   2.
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H8/338 2k Port Darlington pair Figure 16.1 Example of Circuit for Driving a Darlington Pair (5V Version) H8/338 VCC 600 Port 1 or 2 LED Figure 16.2 Example of Circuit for Driving an LED (5V Version) 16.2.2 AC Characteristics The AC characteristics are listed in three tables. Bus timing parameters are given in table 16.6, control signal timing parameters in table 16.7, and timing parameters of the on-chip supporting modules in table 16.8. Rev. 3.
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Table 16.6 Bus Timing Condition A: VCC = 5.0V ±10%, VSS = 0V, φ = 0.5MHz to maximum operating frequency, Ta = −20 to 75°C (regular specifications), Ta = −40 to 85°C (wide-range specifications) Condition B: VCC = 3.0V ±10%, VSS = 0V, φ = 0.5MHz to maximum operating frequency, Ta = −20 to 75°C Condition B Condition A 5MHz 6MHz Min Max Min Max Unit Measurement Conditions Symbol Min Max Clock cycle time tcyc 200 2000 166.7 2000 125 2000 100 2000 ns Fig. 16.
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Table 16.7 Control Signal Timing Condition A: VCC = 5.0V ±10%, VSS = 0V, φ = 0.5MHz to maximum operating frequency, Ta = −20 to 75°C (regular specifications), Ta = −40 to 85°C (wide-range specifications) Condition B: VCC = 3.0V ±10%, VSS = 0V, φ = 0.5MHz to maximum operating frequency, Ta = −20 to 75°C Condition B Condition A 5MHz 6MHz 8MHz 10MHz Item Symbol Min Max Min Max Min Max Min Max Unit Measurement Conditions RES setup time tRESS 300  200  200  200  ns Fig. 16.
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Table 16.8 Timing Conditions of On-Chip Supporting Modules Condition A: VCC = 5.0V ±10%, VSS = 0V, φ = 0.5MHz to maximum operating frequency, Ta = −20 to 75°C (regular specifications), Ta = −40 to 85°C (wide-range specifications) Condition B: VCC = 3.0V ±10%, VSS = 0V, φ = 0.5MHz to maximum operating frequency, Ta = −20 to 75°C Condition B Condition A 5MHz Item FRT Symbol Min 8MHz 10MHz Min Max Min Max Min Max Unit Measurement Conditions tFTOD  150  100  100  100 ns Fig. 16.
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Table 16.8 Timing Conditions of On-Chip Supporting Modules (cont) Condition A: VCC = 5.0V ±10%, VSS = 0V, φ = 0.5MHz to maximum operating frequency, Ta = −20 to 75°C (regular specifications), Ta = −40 to 85°C (wide-range specifications) Condition B: VCC = 3.0V ±10%, VSS = 0V, φ = 0.
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16.2.3 A/D Converter Characteristics Table 16.9 lists the characteristics of the on-chip A/D converter. Table 16.9 A/D Converter Characteristics Condition A: VCC = 5.0V ±10%, AVCC = 5.0V ±10%, VSS = AVSS = 0V, φ = 0.5MHz to maximum operating frequency, Ta = −20 to 75°C (regular specifications), Ta = −40 to 85°C (wide-range specifications) Condition B: VCC = 3.0V ±10%, AVCC = 5.0V ±10%, VSS = AVSS = 0V, φ = 0.
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16.2.4 D/A Converter Characteristics Table 16.10 lists the characteristics of the on-chip D/A converter. Table 16.10 D/A Converter Characteristics Condition A: VCC = 5.0V ±10%, AVCC = 5.0V ±10%, VSS = AVSS = 0V, φ = 0.5MHz to maximum operating frequency, Ta = −20 to 75°C (regular specifications), Ta = −40 to 85°C (wide-range specifications) Condition B: VCC = 3.0V ±10%, AVCC = 5.0V ±10%, VSS = AVSS = 0V, φ = 0.
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16.3.1 Bus Timing (1) Basic Bus Cycle (without Wait States) in Expanded Modes T1 T2 T3 tcyc tCH tCL Ø tcf tAD tcr A15 + A0 tASD tSC tASI tAH AS, RD tACC tRDS tRDH D7 to D0 (Read) tWSD tAS2 tSD tWSW tAH WR tWDD tWDS tWDH D7 to D0 (Write) Figure 16.4 Basic Bus Cycle (without wait states) in Expanded Modes Rev. 3.
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(2) Basic Bus Cycle (with 1 Wait State) in Expanded Modes T2 T1 TW T3 Ø A15 + A0 AS, RD D7 to D0 (Read) WR D7 to D0 (Write) tWTS tWTH tWTS tWTH WAIT Figure 16.5 Basic Bus Cycle (with 1 wait state) in Expanded Modes Rev. 3.
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16.3.2 Control Signal Timing (1) Reset Input Timing Ø tRESS tRESS RES tRESW Figure 16.6 Reset Input Timing (2) Interrupt Input Timing Ø tNMIS tNMIH NMI IRQE (Edge) tNMIS IRQL (Level) tNMIW NMI IRQI Note: i = 0 to 7; IRQE: IRQi when edge-sensed; IRQL: IRQi when level-sensed¶ Figure 16.7 Interrupt Input Timing Rev. 3.
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(3) Clock Settling Timing Ø VCC STBY tOSC1 tOSC1 RES Figure 16.8 Clock Settling Timing (4) Clock Settling Timing for Recovery from Software Standby Mode Ø NMI IRQ tOSC2 ( i = 0, 1, 2) Figure 16.9 Clock Settling Timing for Recovery from Software Standby Mode Rev. 3.
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16.3.3 16-Bit Free-Running Timer Timing (1) Free-Running Timer Input/Output Timing Ø Free-running timer counter Compare-match tFTOD FTOA, FTOB tFTIS FTIA, FTIB, FTIC, FTID Figure 16.10 Free-Running Timer Input/Output Timing (2) External Clock Input Timing for Free-Running Timer Ø tFTCS FTCI tFTCWL tFTCWH Figure 16.11 External Clock Input Timing for Free-Running Timer Rev. 3.
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16.3.4 8-Bit Timer Timing (1) 8-Bit Timer Output Timing Ø Timer counter Compare-match tTMOD TMC0, TMC1 Figure 16.12 8-Bit Timer Output Timing (2) 8-Bit Timer Clock Input Timing Ø tTMCS tTMCS TMCI0 TMCI1 tTMCWL tTMCWH Figure 16.13 8-Bit Timer Clock Input Timing (3) 8-Bit Timer Reset Input Timing Ø tTMRS TMRI0, TMRI1 Timer counter N N' 00 Figure 16.14 8-Bit Timer Reset Input Timing Rev. 3.
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16.3.5 Pulse Width Modulation Timer Timing Ø Timer counter Compare-match tPWOD PW0, PW1 Figure 16.15 PWM Timer Output Timing 16.3.6 Serial Communication Interface Timing (1) SCI Input/Output Timing tScyc Serial clock (SCK0, SCK1) tTXD Transmit data (TXD0, TXD1) tRXS tRXH Receive data (RXD0, RXD1) Figure 16.16 SCI Input/Output Timing (Synchronous mode) (2) SCI Input Clock Timing tSCKW SCK0, SCK1 tScyc Figure 16.17 SCI Input Clock Timing Rev. 3.
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16.3.7 I/O Port Timing T1 T2 T3 Ø tPRS tPRH Port 1 to Port 9 (Input) tPWD Port 1* to Port 9 (Output) Note: * Except P96 and P77 to P70 Figure 16.18 I/O Port Input/Output Timing Rev. 3.
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Appendix A CPU Instruction Set A.
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Instruction Set B @(d:16, Rs16) → Rd8 MOV.B @Rs+, Rd B @Rs16 → Rd8 Rs16+1 → Rs16 MOV.B @aa:8, Rd B @aa:8 → Rd8 MOV.B @aa:16, Rd B @aa:16 → Rd8 MOV.B Rs, @Rd B Rs8 → @Rd16 MOV.B Rs, @(d:16, Rd) B Rs8 → @(d:16, Rd16) MOV.B Rs, @–Rd B Rd16–1 → Rd16 Rs8 → @Rd16 MOV.B Rs, @aa:8 B Rs8 → @aa:8 @aa: 8/16 @(d:8, PC) @@aa Implied @–Rn/@Rn+ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ MOV.B @(d:16, Rs), Rd ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ B @Rs16 → Rd8 0 — 4 ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ B Rs8 → Rd8 MOV.
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Instruction Set (cont) I H N Z V C 4 ↔ ↔ Condition Code Implied @@aa @(d:16, Rn) @–Rn/@Rn+ @aa: 8/16 @(d:8, PC) @Rn Operation #xx: 8/16 Rn Mnemonic Operand Size Addressing Mode/ Instruction Length No. of States Table A.1 MOVFPE@aa:16, Rd — if R4L≠0 then Repeat @R5 → @R6 R5+1 → R5 R6+1 → R6 R4L–1 → R4L Until R4L=0 else next; ADD.B #xx:8, Rd B Rd8+#xx:8 → Rd8 ADD.B Rs, Rd B Rd8+Rs8 → Rd8 ADD.W Rs, Rd W Rd16+Rs16 → Rd16 ADDX.
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Instruction Set (cont) Condition Code I H N Z V C DIVXU.B Rs, Rd B Rd16÷Rs8 → Rd16 (RdH: remainder, RdL: quotient) AND.B #xx:8, Rd B Rd8∧#xx:8 → Rd8 AND.B Rs, Rd B Rd8∧Rs8 → Rd8 OR.B #xx:8, Rd B Rd8⁄#xx:8 → Rd8 OR.B Rs, Rd B Rd8⁄Rs8 → Rd8 XOR.B #xx:8, Rd B Rd8⊕#xx:8 → Rd8 XOR.B Rs, Rd B Rd8⊕Rs8 → Rd8 2 — — NOT.B Rd B Rd → Rd 2 — — SHAL.
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Instruction Set (cont) BSET #xx:3, Rd B (#xx:3 of Rd8) ← 1 BSET #xx:3, @Rd B (#xx:3 of @Rd16) ← 1 BSET #xx:3, @aa:8 B (#xx:3 of @aa:8) ← 1 BSET Rn, Rd B (Rn8 of Rd8) ← 1 BSET Rn, @Rd B (Rn8 of @Rd16) ← 1 BSET Rn, @aa:8 B (Rn8 of @aa:8) ← 1 BCLR #xx:3, Rd B (#xx:3 of Rd8) ← 0 BCLR #xx:3, @Rd B (#xx:3 of @Rd16) ← 0 BCLR #xx:3, @aa:8 B (#xx:3 of @aa:8) ← 0 BCLR Rn, Rd B (Rn8 of Rd8) ← 0 BCLR Rn, @Rd B (Rn8 of @Rd16) ← 0 BCLR Rn, @aa:8 B (Rn8 of @aa:8) ← 0 BNOT #xx:3, Rd B (#xx:3 of Rd
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Instruction Set (cont) B (#xx:3 of Rd8) → C BLD #xx:3, @Rd B (#xx:3 of @Rd16) → C BLD #xx:3, @aa:8 B (#xx:3 of @aa:8) → C BILD #xx:3, Rd B (#xx:3 of Rd8) → C BILD #xx:3, @Rd B (#xx:3 of @Rd16) → C BILD #xx:3, @aa:8 B (#xx:3 of @aa:8) → C BST #xx:3, Rd B C → (#xx:3 of Rd8) BST #xx:3, @Rd B C → (#xx:3 of @Rd16) BST #xx:3, @aa:8 B C → (#xx:3 of @aa:8) BIST #xx:3, Rd B C → (#xx:3 of Rd8) BIST #xx:3, @Rd B C → (#xx:3 of @Rd16) BIST #xx:3, @aa:8 B C → (#xx:3 of @aa:8) BAND #xx:3, Rd B C∧(
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Instruction Set (cont) Condition Code Implied @@aa @(d:16, Rn) @–Rn/@Rn+ @aa: 8/16 @(d:8, PC) Branching Condition @Rn Operation #xx: 8/16 Rn Mnemonic Operand Size Addressing Mode/ Instruction Length I H N Z V C No. of States Table A.
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Instruction Set (cont) SP–2 → SP PC → @SP PC ← @aa:8 @aa: 8/16 @(d:8, PC) @@aa Implied @–Rn/@Rn+ @Rn @(d:16, Rn) 2 Condition Code I H N Z V C — — — — — — 8 RTE — CCR ← @SP SP+2 → SP PC ← @SP SP+2 → SP 2 SLEEP — Transit to sleep mode.
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A.2 Operation Code Map Table A.2 is a map of the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). Some pairs of instructions have identical first bytes. These instructions are differentiated by the first bit of the second byte (bit 7 of the first instruction word). Instruction when first bit of byte 2 (bit 7 of first instruction word) is “0.” Instruction when first bit of byte 2 (bit 7 of first instruction word) is “1.” Rev. 3.
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Rev. 3.0, 09/98, page 306 of 361 XOR AND MOV D E F Note: * The PUSH and POP instructions are identical in machine language to MOV instructions.
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A.3 Number of States Required for Execution The tables below can be used to calculate the number of states required for instruction execution. Table A.3 indicates the number of states required for each cycle (instruction fetch, branch address read, stack operation, byte data access, word data access, internal operation). Table A.4 indicates the number of cycles of each type occurring in each instruction.
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Table A.4 Number of Cycles in Each Instruction Instruction Mnemonic Stack Instruction Branch Addr. Read Operation Fetch K J I ADD ADD.B #xx:8, Rd 1 ADD.B Rs, Rd 1 ADD.W Rs, Rd 1 ADDS ADDS.W #1/2, Rd 1 ADDX ADDX.B #xx:8, Rd 1 ADDX.B Rs, Rd 1 AND.B #xx:8, Rd 1 AND Byte Data Access L AND.
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Table A.4 Number of Cycles in Each Instruction (cont) Byte Data Access L Instruction Mnemonic Stack Instruction Branch Addr.
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Table A.4 Number of Cycles in Each Instruction (cont) Instruction Mnemonic Stack Instruction Branch Addr. Read Operation Fetch K J I BSR BSR d:8 2 BST BTST Byte Data Access L BST #xx:3, Rd 1 BST #xx:3, @Rd 2 2 BST #xx:3, @aa:8 2 2 BTST #xx:3, Rd 1 BTST #xx:3, @Rd 2 1 BTST #xx:3, @aa:8 2 1 BTST Rn, Rd 1 BTST Rn, @Rd 2 1 BTST Rn, @aa:8 2 1 BXOR #xx:3, Rd 1 2 1 BXOR #xx:3, @aa:8 2 1 CMP.B #xx:8, Rd 1 CMP.B Rs, Rd 1 CMP.W Rs, Rd 1 DAA DAA.B Rd 1 DAS DAS.
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Table A.4 Number of Cycles in Each Instruction (cont) Instruction Mnemonic Stack Instruction Branch Addr. Read Operation Fetch K J I Byte Data Access L MOV MOV.B @Rs+, Rd 1 1 MOV.B @aa:8, Rd 1 1 MOVFPE MOV.B @aa:16, Rd 2 1 MOV.B Rs, @Rd 1 1 MOV.B Rs, @(d:16, Rd) 2 1 MOV.B Rs, @-Rd 1 1 MOV.B Rs, @aa:8 1 1 MOV.B Rs, @aa:16 2 1 MOV.W #xx:16, Rd 2 MOV.W Rs, Rd 1 Internal Operation N 2 2 MOV.W @Rs, Rd 1 1 MOV.W @(d:16, Rs), Rd 2 1 MOV.W @Rs+, Rd 1 1 MOV.
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Table A.4 Number of Cycles in Each Instruction (cont) Instruction Mnemonic Stack Instruction Branch Addr. Read Operation Fetch K J I SHAL SHAL.B Rd 1 SHAR SHAR.B Rd 1 SHLL SHLL.B Rd 1 SHLR SHLR.B Rd 1 SLEEP SLEEP 1 STC STC CCR, Rd 1 SUB SUB.B Rs, Rd 1 SUB.W Rs, Rd 1 SUBS.W #1/2, Rd 1 SUBS SUBX XOR XORC SUBX.B #xx:8, Rd 1 SUBX.B Rs, Rd 1 XOR.B #xx:8, Rd 1 XOR.B Rs, Rd 1 XORC #xx:8, CCR 1 Note: All values left blank are zero. Rev. 3.
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Appendix B Register Field B.1 Register Addresses and Bit Names Addr.
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Addr.
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Addr.
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Addr.
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B.2 Register Descriptions Register name Abbreviation of register name Address onto which register is mapped TIER—Timer Interrupt Enable Register Bit No. Bit Initial value Initial value Read/Write 7 ICIAE 0 R/W 6 ICIBE 0 R/W H'FF90 5 ICICE 0 R/W 4 ICIDE 0 R/W 3 2 OCIAE OCIBE 0 0 R/W R/W FRT 1 OVIE 0 R/W 0 — 1 — Name of on-chip supporting module Bit names (abbreviations). Bits marked “—” are reserved.
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SMRSerial Mode Register Bit H'FF88 SCI1 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Clock select 0 0 ø clock 1 ø/4 clock 1 0 ø/16 clock 1 ø/64 clock Multiprocessor mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Stop bit length 0 One stop bit 1 Two stop bits Parity mode 0 Even parity 1 Odd parity Parity enable 0 Transmit: No parity bit added.
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BRRBit Rate Register H'FF89 SCI1 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Constant that determines the bit rate Rev. 3.
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SCRSerial Control Register Bit H'FF8A SCI1 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value 0 0 0 0 0 0 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Clock Enable 0 Internal clock 1 External clock Clock enable 0 0 Asynchronous serial clock not output 1 Asynchronous serial clock output at SCK pin Transmit End Interrupt Enable 0 TSR-empty interrupt request is disabled. 1 TSR-empty interrupt request is enabled.
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TDRTransmit Data Register H'FF8B SCI1 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Transmit data Rev. 3.
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SSRSerial Status Register Bit SCI1 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT 1 0 0 0 1 0 0 R R R/W Initial value * Read/Write H'FF8C R/(W) * R/(W) * R/(W) 0 * R/(W) * R/(W) Multiprocessor Bit transfer 0 Multiprocessor bit = “0” in transmit data. 1 Multiprocessor bit = “1” in transmit data. Multiprocessor Bit 0 Multiprocessor bit = “0” in receive data. 1 Multiprocessor bit = “1” in receive data.
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RDRReceive Data Register H'FF8D SCI1 Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Receive data Rev. 3.
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TIERTimer Interrupt Enable Register Bit H'FF90 FRT 7 6 5 4 3 2 1 0 ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE — Initial value 0 0 0 0 0 0 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W — Overflow Interrupt Enable 0 Overflow interrupt request is disabled. 1 Overflow interrupt request is enabled. Output Compare Interrupt B Enable 0 Output compare interrupt request B is disabled. 1 Output compare interrupt request B is enabled.
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TCSRTimer Control/Status Register Bit H'FF91 FRT 7 6 5 4 3 2 1 0 ICFA ICFB ICFC ICFD OCFA OCFB OVF CCLRA Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/W Counter Clear A 0 FRC count is not cleared. 1 FRC count is cleared by compare-match A. Timer Overflow 0 0 Cleared when CPU reads OVF = "1," then writes "0" in OVF. 1 Set when FRC changes from H'FFFF to H'0000.
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FRC (H and L)Free-Running Counter H'FF92, H'FF93 FRT Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Count value OCRA (H and L)Output Compare Register A H'FF94, H'FF95 FRT Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Continually compared with FRC. OCFA is set to “1” when OCRA=FRC.
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TCRTimer Control Register Bit H'FF96 FRT 7 6 5 4 3 2 1 0 IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Clock enable 0 0 0 Internal clock source: Ø/2 1 1 Internal clock source: Ø/8 1 0 Internal clock source: Ø/32 1 1 External clock source: counted on rising edge Buffer Enable B 0 ICRD is used for input capture D. 1 ICRD is buffer register for input capture B.
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TOCRTimer Output Compare Control Register Bit H'FF97 FRT 7 6 5 4 3 2 1 0 — — — OCRS OEA OEB OLVLA OLVLB Initial value 1 1 1 0 0 0 0 0 Read/Write — — — R/W R/W R/W R/W R/W Output Level B 0 Compare-match B causes “0” output. 1 Compare-match B causes “1” output. Output Level A 0 Compare-match A causes “0” output. 1 Compare-match A causes “1” output. Output Enable B 0 Output compare B output is disabled. 1 Output compare B output is enabled.
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ICRB (H and L)Input Capture Register B H'FF9A, H'FF9B FRT Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Contains FRC count captured on FTIB input. ICRC (H and L)Input Capture Register C H'FF9C, H'FF9D FRT Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Contains FRC count captured on FTIC input, or old ICRA value in buffer mode.
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TCRTimer Control Register Bit H'FFA0 PWM0 7 6 5 4 3 2 1 0 OE OS — — — CKS2 CKS1 CKS0 Initial value 0 0 1 1 1 0 0 0 Read/Write R/W R/W — — — R/W R/W R/W Clock Select (Values When Ø= 10 MHz) Internal Resoclock Freq. lution 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Ø/2 0 Ø/8 1 Ø/32 0 1 Ø/128 0 Ø/256 1 Ø/1024 0 Ø/2048 1 Ø/4096 PWM period 200ns 50µs 800ns 200µs 3.2µs 800µs 12.8µs 3.2ms 25.6µs 6.4ms 102.4µs 25.6ms 204.8µs 51.2ms 409.6µs 102.4ms PWM frequency 20kHz 5kHz 1.
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TCNTTimer Counter H'FFA2 PWM0 Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Count value (runs from H'00 to H'F9, then repeats from H'00) TCRTimer Control Register Bit H'FFA4 PWM1 7 6 5 4 3 2 1 0 OE OW — — — CKS2 CKS1 CKS0 Initial value 0 0 1 1 1 0 0 0 Read/Write R/W R/W — — — R/W R/W R/W Note: Bit functions are the same as for PWM0.
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TCNTTimer Counter H'FFA6 PWM1 Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for PWM0.
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DACRD/A Control Register Bit H'FFAA D/A 7 6 5 4 3 2 1 0 DAOE1 DAOE0 DAE — — — — — Initial value 0 0 0 1 1 1 1 1 Read/Write R/W R/W R/W — — — — — DAOE1 0 0 0 1 1 1 DAOE0 0 1 1 0 0 1 DAE 0 0 1 0 1 — D/A Analog Output Channels 0 and 1 disabled. Channel 0 disabled, channel 1 enabled. Channels 0 and 1 enabled. Channel 0 enabled, channel 1 disabled. Channels 0 and 1 enabled. Channels 0 and 1 enabled.
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P2PCRPort 2 Input Pull-Up Control Register Bit 7 6 5 H'FFAD 4 3 2 Port 2 1 0 P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Port 2 Input Pull-Up Control 0 Input pull-up transistor is off. 1 Input pull-up transistor is on.
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P1DDRPort 1 Data Direction Register Bit 6 7 H'FFB0 5 4 3 Port 1 2 1 0 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Mode 1 Initial value 1 1 1 1 1 1 1 1 Read/Write — — — — — — — — Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Modes 2 and 3 Port 4 Input/Output Control 0 Input port 1 Output port P1DRPort 1 Data Register Bit H'FFB2 Port 1 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P13 P12 P11 P10 Initial value 0 0 0 0 0 0
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P2DDRPort 2 Data Direction Register Bit 6 7 H'FFB1 5 4 3 Port 2 2 1 0 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Mode 1 Initial value 1 1 1 1 1 1 1 1 Read/Write — — — — — — — — Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Modes 2 and 3 Port 2 Input/Output Control 0 Input port 1 Output port P2DRPort 2 Data Register Bit H'FFB3 Port 2 7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21 P20 Initial value 0 0 0 0 0 0
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P3DRPort 3 Data Register Bit H'FFB6 Port 3 7 6 5 4 3 2 1 0 P37 P36 P35 P34 P33 P32 P31 P30 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W P4DDRPort 4 Data Direction Register Bit 7 6 H'FFB5 5 4 3 Port 4 2 1 0 P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Port 4 Input/Output Control 0 Input port 1 Output port P4DRPort 4 Data Register Bit H'FFB7
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P5DRPort 5 Data Register Bit H'FFBA Port 5 7 6 5 4 3 2 1 0 — — — — — P52 P51 P50 Initial value 1 1 1 1 1 0 0 0 Read/Write — — — — — R/W R/W R/W P6DDRPort 6 Data Direction Register Bit 7 6 H'FFB9 5 4 3 Port 6 2 1 0 P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Port 6 Input/Output Control 0 Input port 1 Output port P6DRPort 6 Data Register Bit H'FFBB Port 6 7 6 5 4
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P8DDRPort 8 Data Direction Register Bit 7 — H'FFBD 5 6 4 3 2 Port 8 1 0 P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR Initial value 1 0 0 0 0 0 0 0 Read/Write — W W W W W W W Port 8 Input/Output Control 0 Input port 1 Output port P8DRPort 8 Data Register Bit H'FFBF Port 8 7 6 5 4 3 2 1 0 — P86 P85 P84 P83 P82 P81 P80 Initial value 1 0 0 0 0 0 0 0 Read/Write — R/W R/W R/W R/W R/W R/W R/W P9DDRPort 9 Data Direction Register Bit 7 6
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P9DRPort 9 Data Register Bit H'FFC1 Port 9 7 6 5 4 3 2 1 0 P96 P96 P95 P94 P93 P92 P91 P90 Initial value 0 * 0 0 0 0 0 0 Read/Write R/W R R/W R/W R/W R/W R/W R/W Notes: * Depends on the level of pin P96.
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SYSCRSystem Control Register Bit H'FFC4 System Control 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 — NMIEG DPME RAME Initial value 0 0 0 0 1 0 0 1 Read/Write R/W R/W R/W R/W — R/W R/W* R/W RAM Enable 0 On-chip RAM is disabled. 1 On-chip RAM is enabled. Dual-Port RAM Enable Not supported. (Do not set to “1.”) NMI Edge 0 Falling edge of NMI is detected. 1 Rising edge of NMI is detected.
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MDCRMode Control Register Bit H'FFC5 7 6 — — — Initial value 1 1 Read/Write — — System Control 3 2 1 0 — — — MDS1 MDS0 1 0 0 1 * * — — — — R/W R/W 5 4 Mode Select Bits Value at mode pins.
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TCRTimer Control Register Bit H'FFC8 7 6 5 4 3 2 1 0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TMR0 Clock Select TCR STCR CKS2 CKS1 CKS0 ICKS1 ICKS0 0 0 0 — — Description Timer stopped 0 0 1 — 0 Ø/8 internal clock, falling edge 0 0 1 — 1 Ø/2 internal clock, falling edge 0 1 0 — 0 Ø/64 internal clock, falling edge 0 1 0 — 1 Ø/32 internal clock, falling edge 0
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TCSRTimer Control/Status Register Bit 7 6 5 H'FFC9 TMR0 4 3 2 1 0 OS2*2 OS1*2 OS0*2 CMFB CMFA OVF — OS3*2 Initial value 0 0 0 1 0 0 0 0 Read/Write R/(W)*1 R/(W)*1 R/(W)*1 — R/W R/W R/W R/W Output Select 0 0 No change on compare-match A. 0 1 Output “0” on compare-match A. 1 0 Output “1” on compare-match A. 1 1 Invert (toggle) output on compare-match A. Output Select 0 0 No change on compare-match B. 0 1 Output “0” on compare-match B. 1 0 Output “1” on compare-match B.
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TCORATime Constant Register A H'FFCA TMR0 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W The CMFA bit is set to “1” when TCORA= TCNT. TCORBTime Constant Register B Bit 7 6 H'FFCB 5 4 3 2 TMR0 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W The CMFB bit is set to “1” when TCORB= TCNT.
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TCRTimer Conrol Register Bit H'FFD0 TMR1 7 6 5 4 3 2 1 0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Clock Select TCR STCR CKS2 CKS1 CKS0 ICKS1 ICKS0 Description 0 0 0 — — Timer stopped 0 0 1 0 — Ø/8 internal clock, falling edge 0 0 1 1 — Ø/2 internal clock, falling edge 0 1 0 0 — Ø/64 internal clock, falling edge 0 1 0 1 — Ø/128 internal clock, falling edge 0
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TCSRTimer Control/Status Register Bit H'FFD1 TMR1 7 6 5 4 3 2 1 0 CMFB CMFA OVF — OS3*2 OS2*2 OS1*2 OS0*2 Initial value 0 0 0 1 0 0 0 0 Read/Write R/(W)*1 R/(W)*1 R/(W)*1 — R/W R/W R/W R/W Note: Bit functions are the same as for TMR0. *1 Software can write a “0” in bits 7 to 5 to clear the flags, but cannot write a “1” in these bits. *2 When all four bits (OS3 to OS0) are cleared to “0,” output is disabled.
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SMRSerial Mode Register Bit H'FFD8 SCI0 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Clock select 0 0 ø clock 1 ø/4 clock 1 0 ø/16 clock 1 ø/64 clock Multiprocessor mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Stop bit length 0 One stop bit 1 Two stop bits Parity mode 0 Even parity 1 Odd parity Parity enable 0 Transmit: No parity bit added.
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BRRBit Rate Register H'FFD9 SCI0 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Constant that determines the bit rate Note: Bit functions are the same as for SCI1. Rev. 3.
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SCRSerial Control Register Bit H'FFDA SCI0 7 6 5 4 3 2 1 0 CKE0 TIE RIE TE RE MPIE TEIE CKE1 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Clock Enable 1 0 Internal clock 1 External clock Clock enable 0 0 Asynchronous serial clock not output 1 Asynchronous serial clock output at SCK pin Transmit End Interrupt Enable 0 TSR-empty interrupt request is disabled. 1 TSR-empty interrupt request is enabled.
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TDRTransmit Data Register H'FFDB SCI0 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Transmit data Note: Bit functions are the same as for SCI1. Rev. 3.
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SSRSerial Status Register Bit SCI0 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT 1 0 0 0 1 0 0 R R R/W Initial value * Read/Write H'FFDC R/(W) * R/(W) * R/(W) 0 * R/(W) * R/(W) Multiprocessor Bit transfer 0 Multiprocessor bit = “0” in transmit data. 1 Multiprocessor bit = “1” in transmit data. Multiprocessor Bit 0 Multiprocessor bit = “0” in receive data. 1 Multiprocessor bit = “1” in receive data.
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RDRReceive Data Register H'FFDD SCI0 Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Receive data Note: Bit functions are the same as for SCI1. ADDRnA/D Data Register n (n = A, B, C, D) H'FFE0, H'FFE2, H'FFE4, H'FFE6 A/D Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R A/D conversion result Rev. 3.
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ADCSRA/D Control/Status Register Bit H'FFE8 A/D 7 6 5 4 3 2 1 0 ADF ADIE ADST SCAN CKS CH2 CH1 CH0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/W R/W R/W R/W R/W R/W R/W Clock Select CH2 CH1 CH0 Single mode Scan mode 0 0 0 AN0 AN0 0 1 AN1 AN0, AN1 1 0 AN2 AN0 to AN2 1 1 AN3 AN0 to AN3 0 0 AN4 AN4 0 1 AN5 AN4, AN5 1 0 AN6 AN4 to AN6 1 1 AN7 AN4 to AN7 1 Clock Select 0 Conversion time = 242 states (max) 1 Conversion time = 122 s
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ADCRA/D Control Register Bit H'FFEA A/D 7 6 5 4 3 2 1 0 TRGE — — — — — — CHS Initial value 0 1 1 1 1 1 1 0 Read/Write R/W — — — — — — R/W Reserved bit. Trigger Enable 0 ADTRG is disabled. 1 ADTRG is enabled. A/D conversion can be started by external trigger, or by software. Rev. 3.
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Appendix C Pin States C.1 Pin States in Each Mode Table C.1 Pin States Pin Name MCU Mode Reset Hardware Standby Software Standby 1 Low 3-State Low 2 3-State P17 − P10 A7 − A0 Low if DDR = 1, Prev. state if DDR = 0 3 P27 − P20 A15 − A8 Low 2 3-State 3-State 1 Low if DDR = 1, Prev. state if DDR = 0 I/O port Prev. state A15 − A8 (Addr. output Addr. output or pins: last address input port accessed) Prev. state 3-State 3-State I/O port 3-state 3-State D7 − D0 Prev. state Prev.
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Table C.1 Pin States (cont) Pin Name MCU Mode Reset Hardware Standby Software Standby Sleep Mode Normal Operation P67 − P60 1 3-State 3-State Prev. state* Prev. state I/O port 3-State 3-State 3-State 3-State Input port 3-State 3-State Prev. state* Prev. state I/O port 3-State 3-State 3-State 3-State WAIT Prev. state Prev.
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Appendix D Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode (1) To retain RAM contents when the RAME bit in SYSCR is cleared to 0, drive the RES signal low 10 system clock cycles before the STBY signal goes low, as shown below. RES must remain low until STBY goes low (minimum delay from STBY low to RES high: 0 ns).
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Appendix E Package Dimensions Figure E.1 shows the dimensions of the CG-84 package. Figure E.2 shows the dimensions of the CP-84 package. Figure E.3 shows the dimensions of the FP-80A package. 29.21 ± 0.38 Unit: mm 4.03 Max φ 8.89 12 32 33 0.635 11 1 84 75 53 54 74 2.16 1.27 1.27 Hitachi Code JEDEC EIAJ Weight (reference value) CG-84 — — 8.96 g Figure E.1 Package Dimensions (CG-84) Rev. 3.
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Unit: mm 30.23 +0.12 –0.13 29.28 74 54 53 84 1 11 0.20 M 1.94 1.27 *0.42 ± 0.10 0.38 ± 0.08 28.20 ± 0.50 *Dimension including the plating thickness Base material dimension 0.90 0.75 2.55 ± 0.15 33 32 12 4.40 ± 0.20 30.23 +0.12 –0.13 75 28.20 ± 0.50 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) Figure E.2 Package Dimensions (CP-84) Rev. 3.0, 09/98, page 360 of 361 CP-84 Conforms Conforms 6.
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17.2 ± 0.3 Unit: mm 14 60 41 40 0.65 17.2 ± 0.3 61 80 21 1 0.10 *Dimension including the plating thickness Base material dimension *0.17 ± 0.05 0.15 ± 0.04 3.05 Max 0.83 2.70 0.12 M 0.10 +0.15 –0.10 *0.32 ± 0.08 0.30 ± 0.06 20 1.6 0° – 8° 0.8 ± 0.3 Hitachi Code JEDEC EIAJ Weight (reference value) FP-80A — Conforms 1.2 g Figure E.3 Package Dimensions (FP-80A) Rev. 3.
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H8/338 Series Hardware Manual Publication Date: 1st Edition, July 1992 3rd Edition, September 1998 Published by: Electronic Devices Sales & Marketing Group Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group UL Media Co., Ltd. Copyright © Hitachi, Ltd., 1992. All rights reserved. Printed in Japan.