Technical information

10
Section 3 Notes on Use
3.1 I/O Register Differences between Actual MCU and E6000
In the E6000, one evaluation chip emulates several types of MCU. Therefore, there are some
differences in I/O registers between an actual MCU and the E6000. Note these differences when
accessing the I/O registers.
I/O port is in the input state at default. The I/O register contents indicate the emulator port status.
When the user system interface cable is not connected, the read value is 1 due to the emulator's
pull-up resistors.
In E6000, accesses to the following registers for controlling the flash memory are invalid.
•
RAM control register (RAMCR)
•
Flash memory control register (FLMCR)
•
Erase block register 1 (EBR1)
•
Erase block register 2 (EBR2)
When a target MCU that has flash memory is emulated, do not allow the /RESO output of the
watchdog timer.
Note: Although the external output of the reset signal is enabled or disabled by the reset-output
enable bit in the watchdog timer control register, this bit should not be enabled because the
internal registers are reset by the reset signal. At reset, a reset signal reinitializes the reset-
output enable bit to its disabled state.
3.2. Access to On-Chip RAM Area
By using the RAME bit in SYSCR, RAM area can be used as external address area. Note that only
User (user memory) can be accessed as external address and not Emulator (option memory). In
this case, internal RAM is set in the Memory Mapping. Do not specify Emulator (option memory)
for the area including internal RAM.
3.3 Support of Flash Memory
The E6000 does not emulate the flash memory control operation in the MCU.