Technical information

9
P70 to P77 (pins used for AN0 to AN7 and DA0 to DA1), AVcc, AVss and Vref:
Figure 2.6 User System Interface Circuit for P70 to P77, AVcc, AVss and Vref Signals
/
IRQ0–/IRQ5 and /WAIT:
The /IRQ0 to /IRQ5 and /WAIT signals are input to the MCU and
also to the trace acquiring circuit. Therefore, the rising and falling time of these signals must be
within 8 ns/V or shorter.
Figure 2.7 IRQ0
–
IRQ5 and /WAIT User System Interface Circuit