Product data

HD404818 Series
94
During Transmit Clock Input
Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes
Transmit clock cycle time t
Scyc
SCK 1
t
cyc
/
t
subcyc
1, 4
Transmit clock high and low
widths
t
SCKH
,
t
SCKL
SCK 0.5 t
Scyc
1
Transmit clock rise and fall
times
t
SCKr
,
t
SCKf
SCK 200 ns 1
Serial output data delay time t
DSO
SO 500 ns 1, 2
Serial input data setup time t
SSI
SI 300 ns 1
Serial input data hold time t
HSI
SI 300 ns 1
Transmit clock completion
detect time
t
SCKHD
SCK 1
t
cyc
/
t
subcyc
1, 2,
3, 4
Notes: 1. See figure 51.
2 See figure 52.
3. The transmit clock completion detect time is the high level period after 8 pulses of transmit
clocks are input. The serial interrupt request flag is not set if the next transmit clock is input
before the transmit clock completion detect time has passed.
4. t
subcyc
is applied when the MCU is in subactive mode. t
subcyc
= 244.14 µs (for a 32.768-kHz crystal
oscillator).
t
CPr
t
CPf
V
CC
– 0.3 V
0.3 V
OSC
1
t
CPH
t
CPL
1/f
CP
Figure 48 Oscillator Timing
0.9V
CC
0.1V
CC
INT
0
, INT
1
t
IH
t
IL
Figure 49 Interrupt Timing
RESET
t
RSTf
t
RSTH
0.9V
CC
0.1V
CC
Figure 50 Reset Timing