Product data

HD404818 Series
85
Serial Interface Timing Characteristics
During Transmit Clock Output (HD404812, HD404814, HD404816, HD404818: V
CC
= 4 to 6 V;
HD4074818: V
CC
= 4 to 5.5 V; GND = 0 V, T
a
= –20°C to +75°C, unless otherwise specified)
Item Symbol Pin Min Typ Max Unit Test Condition Notes
Transmit clock cycle time t
Scyc
SCK 1
t
cyc
/
t
subcyc
1, 2, 4
Transmit clock high and
low widths
t
SCKH,
t
SCKL
SCK 0.5 t
Scyc
1, 2
Transmit clock rise and
fall times
t
SCKr,
t
SCKf
SCK 100 ns 1, 2
Serial output data delay
time
t
DSO
SO 300 ns 1, 2
Serial input data setup
time
t
SSI
SI 200 ns 1
Serial input data hold time t
HSI
SI 150 ns 1
During Transmit Clock Input
Item Symbol Pin Min Typ Max Unit Test Condition Notes
Transmit clock cycle time t
Scyc
SCK 1
t
cyc
/
t
subcyc
1, 4
Transmit clock high and
low widths
t
SCKH,
t
SCKL
SCK 0.5 t
Scyc
1
Transmit clock rise and
fall times
t
SCKr,
t
SCKf
SCK 100 ns 1
Serial output data delay
time
t
DSO
SO 300 ns 1, 2
Serial input data setup
time
t
SSI
SI 200 ns 1
Serial input data hold time t
HSI
SI 150 ns 1
Transmit clock completion
detect time
t
SCKHD
SCK 1
t
cyc
/
t
subcyc
1,2, 3, 4
Notes: 1. See figure 46.
2. See figure 47.
3. The transmit clock completion detect time is the high level period after 8 pulses of transmit
clocks are input. The serial interrupt request flag is not set if the next transmit clock is input
before the transmit clock completion detect time has passed.
4. The unit t
subcyc
is applied when the MCU is in subactive mode. t
subcyc
= 244.14 µs (for a 32.768-
kHz crystal oscillator).