Product data

HD404818 Series
65
Table 29 LCD Frame Frequency
LMR
Static Bit 3 Bit 2 Bit 3 Bit 2 Bit 3 Bit 2 Bit 3 Bit 2
Instruction
cycle time
00011011
CL0 CL1 CL2 CL3*
10 µs 512 Hz 390.6 Hz 48.8 Hz 24.4 Hz/64 Hz
1 µs 512 Hz 3906 Hz 488Hz 244 Hz/64 Hz
LMR
1/2 Duty Cycle Bit 3 Bit 2 Bit 3 Bit 2 Bit 3 Bit 2 Bit 3 Bit 2
Instruction
cycle time
00011011
CL0 CL1 CL2 CL3*
10 µs 256 Hz 195.3 Hz 24.4 Hz 12.2 Hz/32 Hz
1 µs 256 Hz 1953 Hz 244 Hz 122 Hz/32 Hz
LMR
1/3 Duty Cycle Bit 3 Bit 2 Bit 3 Bit 2 Bit 3 Bit 2 Bit 3 Bit 2
Instruction
cycle time
00011011
CL0 CL1 CL2 CL3*
10 µs 170.6 Hz 130.2 Hz 16.3 Hz 8.1 Hz/21.3 Hz
1 µs 170.6 Hz 1302 Hz 162.6 Hz 81.3 Hz/21.3 Hz
LMR
1/4 Duty Cycle Bit 3 Bit 2 Bit 3 Bit 2 Bit 3 Bit 2 Bit 3 Bit 2
Instruction
cycle time
00011011
CL0 CL1 CL2 CL3*
10 µs 128 Hz 97.7 Hz 12.2 Hz 6.1 Hz/16 Hz
1 µs 128 Hz 977 Hz 122 Hz 61 Hz/16 Hz
Note: * Division ratio differs depending on the value of bit 3 of timer mode register A
(TMA3 = 0/TMA3 = 1).
If TMA3 = 0, CL3 = fcyc x duty cycle/4096; if TMA3 = 1, CL3 = 32.768 kHz x duty cycle/512.