Product data

HD404818 Series

Table 27 LCD Control Register

LCR

BIT 2

Watch Mode/ Subactive Mode

Display

LCR

BIT 1 Power Switch On/Off

LCR

BIT 0 Blank/ Display

0 Off 0 Off 0 Blank

1 On 1 On 1 Display

Note: With the LCD in watch mode, use the divider output of the 32-kHz oscillator as an LCD clock and set

LCR bit 2 to 1. When the system oscillator divider output is used as an LCD clock, set LCR bit 2 to

Table 28 LCD Duty-Cycle/Clock Control Register

LMR

Bit 3 Bit 2 Bit 1 Bit 0 Duty Cycle Select/Input Clock Select

— — 0 0 1/4 duty cycle

— — 0 1 1/3 duty cycle

— — 1 0 1/2 duty cycle

— — 1 1 Static

0 0 — — CL0 (32.768 kHz/64; when 32.768-kHz oscillator is used)

0 1 — — CL1 (f

cyc

/256)

1 0 — — CL2 (f

cyc

/2048)

1 1 — — CL3 (Refer to table 29)

Note: f

cyc

is the system oscillator divider output.

210

LCR (LCD control register) ADR = $013

Blank/display

Power switch on/off

(not used)

Display on/off in watch mode

Duty cycle selection

Input clock selection

3210

LMR (LCD mode register) ADR = $014

Figure 36 LCD Control Register