Product data

HD404818 Series
58
(IFS ← 1)
Octal counter = 000
transmit clock disable
STS waiting state
Transmit clock
8 external transmit clocks
STS instruction
Transmit clock wait state
(Octal counter = 000)
Transfer state
(Octal counter
≠ 000)
Write to SMR
STS instruction
SMR write
8 internal transmit clocks
(IFS ← 1)
(IFS ← 1)
Figure 30 Serial Interface Operation States
Example of Transmit Clock Error Detection: The serial interface malfunctions when the transmit clock
is disturbed by external noise. In this case, transmit clock errors can be detected by the procedure shown in
figure 31.
If more than 8 transmit clocks are applied in the transmit clock wait state, the state of the serial interface
shifts in the following sequence: transfer state, transmit clock wait state, and transfer state again. The serial
interrupt request flag should be reset before entering into the STS waiting state by writing data to SMR.
This procedure causes the serial interface request flag to be set again.