Product data
HD404818 Series
56
Serial Interface
The serial interface transmits/receives 8-bit data serially. It consists of the serial data register, the serial
mode register, port mode register A, the octal counter, and the selector (figure 29). Pin R0
0
/SCK and the
transmit clock signal are controlled by the serial mode register. The data of the serial data register can be
written and read by software. The data in the serial data register can be shifted synchronously with the
transmit clock signal.
The STS instruction starts serial interface operations and resets the octal counter to $0. The octal counter
starts to count at the falling edge of the transmit clock signal (SCK) and increments by one at the rising
edge of the S C K. When the octal counter is reset to $0 after eight transmit clock signals, or when a
transmit/receive operation is discontinued by resetting the octal counter, the serial interrupt request flag will
be set.
Internal data bus
÷2
÷8
÷32
÷128
÷512
÷2048
Port mode
register
(PMRA)
SCK
Selector
System
clock
Prescaler S (PSS)
I/O
control
logic
3
Serial mode
register
(SMR)
Clock
Serial data
register (SR)
Serial interrupt
request flag
(IFS)
Selector
1/2
SI
SO
Octal
counter (OC)
I/O
control
logic
Transfer
control
signal
f
cyc
/f
sub
(t
cyc
/t
subcyc
)
Figure 29 Serial Interface Block Diagram