Product data

HD404818 Series

5. The division ratio must not be modified during time base mode operation, otherwise an overflow

cycle error will occur.

Timer Mode Register C (TMC: $00D): Timer mode register C is a 4-bit write-only register which selects

the auto-reload function, input clock source, and prescaler divide ratio, as table 23 shows. Timer mode

The contents of timer mode register C will change in the second instruction cycle after a write instruction to

TMC. Therefore, it is required to initialize timer C after the contents of timer mode register C have been

changed completely.

Timer B (TCBL: $00A, TCBU: $00B, TLRL: $00A, TLRU: $00B): Timer B consists of an 8-bit write-

only timer load register, and an 8-bit read-only timer counter. Each of them has low-order digits (TCBL:

$00A, TLRL: $00A) and high-order digits (TCBU: $00B, TLRU: $00B). (Refer to figure 26.)

Timer counter B can be initialized by writing data into timer load register B. In this case, write the low-

order digits first, and then the high-order digits. The timer counter is initialized when the high-order digit

is written. The timer load register is initialized to $00 by MCU reset.

The counter value of timer B can be obtained by reading timer counter B. In this case, read the high-order

digits first, and then the low-order digits. The count value of the low-order digit is obtained when the high-

order digit is read.

Timer C (TCCL: $00E, TCCU: $00F, TCRL: $00E, TCRU: $00F): Timer C consists of the 8-bit write-

only timer load register and the 8-bit read-only timer counter. These individually consist of low-order digits

(TCCL: $00E, TCRL: $00E) and high-order digits (TCCU: $00F, TCRU: $00F). The operation mode of

timer C is the same as that of timer B.

Table 22 Timer Mode Register B

TMB3 Auto-Reload Function

0No

1 Yes

TMB2 TMB1 TMB0 Prescaler Divide Ratio, Clock Input Source

00 0 ÷ 2048

00 1 ÷ 512

01 0 ÷ 128

01 1 ÷ 32

10 0 ÷ 8

10 1 ÷ 4

11 0 ÷ 2

11 1 INT

(external event input)