Product data

HD404818 Series
13
0
1
2
3
Bit 3 Bit 2 Bit 1 Bit 0
IM0
(IM of INT )
0
IF0
(IF of INT )
0
RSP
(Reset SP bit)
IE
(Interrupt enable flag)
IMTA
(IM of timer A)
IFTA
(IF of timer A)
IM1
(IM of INT )
1
IF1
(IF of INT )
1
IMTC
(IM of timer C)
IFTC
(IF of timer C)
IMTB
(IM of timer B)
IFTB
(IF of timer B)
Not used Not used
IMS
(IM of serial)
IFS
(IF of serial)
$000
$001
$002
$003
32
DTON
Direct transfer on flag
Not used
WDON
(Watchdog on flag)
LSON
(Low speed on flag)
Not used
$020
$021
$023
IF:
IM:
IE:
SP:
Note:
Bits in the interrupt control bits area and register flag area are set by the SEM or SEMD
instruction, reset by the REM or REMD instruction, and tested by the TM or TMD instruction.
Other instructions have no effect.
However, note the following usage limitations of RAM bit manipulation instructions.
Interrupt request flag
Interrupt mask
Interrupt enable flag
Stack pointer
IF
RSP
WDON
DTON
SEM/SEMD
Not executed
Not executed
Allowed
Not executed in active mode
Used in subactive mode
REM/REMD
Allowed
Allowed
Not executed
Allowed
TM/TMD
Allowed
Inhibited
Inhibited
Allowed
Note: WDON is reset only by MCU reset.
DTON is always reset in active mode.
If the TM or TMD instruction is executed for the inhibited bits or non-existing bits, the value in
ST becomes invalid.
Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas