Product data
HD404818 Series
12
0
$000 $000
63
64
80
112
959
960
1023
$03F
$040
$050
$070
$3FF
4
5
6
7
0
1
2
3
12
13
14
15
8
9
10
11
16
17
32
35
48
18
19
20
49
50
51
63
$001
$002
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
$00F
$010
$011
$012
$013
$014
$020
$023
$030
$031
$032
$033
$03B
$03C
$03D
$03F
$00A
$00B
$00E
$00F
W
W
R/W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
W
R/W
R/W
R/W
R/W
R/W
R/W
$100
$2CF
61
59
60
$3BF
$3C0
$2CF
RAM-mapped registers
Memory registers (MR)
LCD display area (32 digits)
Data (144 digits)
Data (464 digits 2)
V = 0 (bank 0)
V = 1 (bank 1)
Not used
Stack (64 digits)
Interrupt control bits area
Port mode register A (PMRA)
Serial mode register (SMR)
Serial data register lower (SRL)
Serial data register upper (SRU)
Timer mode register A (TMA)
Timer mode register B (TMB)
Timer B (TCBL/TLRL)
(TCBU/TLRU)
Miscellaneous register (MIS)
Timer mode register C (TMC)
Timer C (TCCL/TCRL)
(TCCU/TCRU)
Not used
Not used
Port mode register B (PMRB)
LCD control register (LCR)
LCD mode register (LMR)
Not used
Register flag area
Not used
Port R0 DCR (DCR0)
Port R1 DCR (DCR1)
Port R2 DCR (DCR2)
Port R3 DCR (DCR3)
Not used
Port D –D DCR (DCRB)
Port D –D DCR (DCRC)
Port D –D DCR (DCRD)
Not used
V register (V-REG)
03
47
89
Data (464 digits)
V = 1 (bank 1)
Data (464 digits)
V = 0 (bank 0)
Note: Do not use any area labelled "Not used".
10
11
14
15
Timer counter B lower
(TCBL)
Timer counter B upper
(TCBU)
Timer counter C lower
(TCCL)
Timer counter C upper
(TCCU)
Timer load register B lower
(TLRL)
Timer load register B upper
(TLRU)
Timer load register C lower
(TCRL)
Timer load register C upper
(TCRU)
R:
W:
R/W:
×
$100
Read only
Write only
Read/write
The data area has two banks:
bank 0 (V = 0) and bank 1 (V = 1)
Figure 2 RAM Memory Map (1,184-digit × 4-bit)