Product data

HD404818 Series
9
Block Diagram
Internal address bus
System control circuit
RAM
(1,184 4 bits)×
W (2 bits)
X (4 bits)
SPX (4 bits)
Y (4 bits)
SPY (4 bits)
CA
(1 bit)
ST
(1 bit)
A (4 bits)
B (4 bits)
SP (10 bits)
Instruction
decoder
PC (14 bits)
ROM
(2,048 × 10 bits)
(4,096 × 10 bits)
(6,144 × 10 bits)
(8,192 × 10 bits)
D port
ALU
CPU
INT
0
INT
1
Timer B
Timer C
TIMO
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
10
D
11
R0 port
R0
0
R0
1
R0
2
R0
3
R1 port
R1
0
R1
1
R1
2
R1
3
R2 port
R2
0
R2
1
R2
2
R2
3
R3 port
R3
0
R3
1
R3
2
R3
3
RESET TEST OSC OSC X1 X2 V
CC
GND
Timer A
External
interrupt
control
circuit
Internal data bus Internal data bus
High-
current
pins
LCD
driver
circuit
V
1
V
2
V
3
COM1
COM2
COM3
COM4
SEG1
SEG2
SEG3
SEG31
SEG32
VC
ref
Compa-
rator
Serial
interface
SI
SO
SCK
: Data bus
: Signal lines
1 2
COMP
0
COMP
1
D
12
D
13