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HD404818 Series 4-Bit Single-Chip Microcomputer Preliminary Rev. 2.0 Sept. 1998 Description T he H D4 04 81 8 Se ri es of 4-bit single-chip HMCS400 series microcomputers provide high program productivity. It incorporates a large size memory, LCD controller/driver, voltage comparator, and 32-kHz watch oscillator circuit. The HD404818 Series has both standard voltage versions and low voltage versions available. The standard voltage versions operate at 4.0 V to 6.0 V (mask ROM version) and 4.0 V to 5.
HD404818 Series • Subroutine stack up to 16 levels, including interrupts • Instruction cycle time: 1 µs (fOSC = 4 MHz for HD404812/HD404814/HD404816/HD404818/HD4074818) 5 µs (fOSC = 800 kHz for HD40L4812/HD40L4814/HD40L4816/HD40L4818/HD407L4818) • Four low-power dissipation modes Standby mode Stop mode Watch mode Subactive mode • Internal oscillator: Main clock: Can be driven by ceramic oscillator, crystal oscillator, or external clock Subclock: 32.
HD404818 Series Ordering Information Type Mask ROM Supply Voltage Product Name Model Name ROM (Word) Clock Frequency Package Standard (4.0 to 6.0 V) HD404812 HD404812FS 2,048 4 FP-80B HD404814 HD404816 HD404818 Low-voltage operation HD40L4812 (2.7 to 6.0 V) HD40L4814 HD40L4816 HD40L4818 ZTAT Standard (4.0 to 5.5 V) Low-voltage operation (3.0 to 5.
HD404818 Series 4 61 62 63 64 65 66 60 2 59 3 58 4 57 5 56 6 55 7 54 8 53 9 10 52 51 TFP-80 FP-80A 11 50 40 39 38 37 36 35 34 33 32 41 30 31 43 42 20 29 44 18 19 28 45 17 27 46 16 26 47 15 25 48 14 24 49 13 23 12 (top view) (top view) 67 68 69 71 70 72 73 74 75 76 77 78 79 80 1 22 D4 D5 D6 D7 D8 D9 D10 VCref /D11 COMP0/D12 COMP1/D13 TEST X1 X2 GND SCK/R0 0 SI/R0 1 SO/R0 2 R0 3 R1 0 R1 1 21 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26
HD404818 Series Pin Description Pin Number Pin Number FP-80B FP-80A, TFP-80 Pin Name I/O FP-80B FP-80A, TFP-80 Pin Name I/O 1 79 D2 I/O 31 29 R3 2/INT0 I/O 2 80 D3 I/O 32 30 R3 3/INT1 I/O 3 1 D4 I/O 33 31 SEG1 O 4 2 D5 I/O 34 32 SEG2 O 5 3 D6 I/O 35 33 SEG3 O 6 4 D7 I/O 36 34 SEG4 O 7 5 D8 I/O 37 35 SEG5 O 8 6 D9 I/O 38 36 SEG6 O 9 7 D10 I 39 37 SEG7 O 10 8 D11/VCref I 40 38 SEG8 O 11 9 D12/COMP0 I 41 39 SEG9 O
HD404818 Series Pin Number Pin Number FP-80B FP-80A, TFP-80 Pin Name I/O FP-80B FP-80A, TFP-80 Pin Name I/O 61 59 SEG29 O 71 69 V3 62 60 SEG30 O 72 70 NUMO 63 61 SEG31 O 73 71 NUMO 64 62 SEG32 O 74 72 NUMG 65 63 COM1 O 75 73 VCC 66 64 COM2 O 76 74 OSC 1 I 67 65 COM3 O 77 75 OSC 2 O 68 66 COM4 O 78 76 RESET I 69 67 V1 79 77 D0 I/O 70 68 V2 80 78 D1 I/O Note: I/O: Input/output pin, I: Input pin, O: Output pin, NUMO: Open, NUMG:
HD404818 Series Pin Functions Power Supply VCC: Apply the VCC power supply voltage to this pin. GND: Connect to ground. TEST: For test purposes only. Connect it to VCC. RESET: MCU reset pin. Refer to the Reset section for details. NUMG: Non-user pin. Connect it to GND. NUMO: Non-user pin. Do not connect it to any lines. Oscillators OSC 1, OSC2: Internal oscillator input pins. They both can be connected to a crystal, ceramic resonator, or external oscillator circuit.
HD404818 Series LCD Driver/Controller V1, V2, V3: Power supply pins for the LCD driver. Since the LCD driving resistors are provided internally, no lines should be connected to these pins. The voltage on each pin is VCC ≥ V 1 ≥ V2 ≥ V3 ≥ GND. See the Liquid Crystal Display section for details. COM1 to COM4: Common signal output pins for the LCD display. See the Liquid Crystal Display section for details. SEG1 to SEG32: Segment signals output pins for the LCD display.
HD404818 Series VCC GND OSC 1 OSC 2 X1 X2 RESET TEST Block Diagram D port D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 R0 port R00 R01 R02 R03 R1 port External interrupt control circuit R10 R11 R12 R13 R2 port INT0 INT1 R20 R21 R22 R23 R3 port System control circuit R30 R31 R32 R33 RAM (1,184 × 4 bits) W (2 bits) Timer A X (4 bits) Timer B VCref COMP0 COMP1 SPY (4 bits) ALU CPU Comparator Internal data bus Serial interface Internal address bus SI SO SCK Y (4 bits) Timer C Inte
HD404818 Series Memory Map ROM Memory Map The ROM is described in the following paragraphs with the ROM memory map in figure 1.
HD404818 Series RAM Memory Map The MCU also contains a 1,184-digit × 4-bit RAM as the data and stack area. In addition to these areas, interrupt control bits and special function registers are mapped on the RAM memory space. The RAM memory map (figure 2) is described in the following paragraphs. Interrupt Control Bits Area ($000 to $003): The interrupt control bits area (figure 3) is used for interrupt control. It is accessible only by RAM bit manipulation instructions.
HD404818 Series 0 $000 RAM-mapped registers 63 64 80 112 Memory registers (MR) LCD display area (32 digits) $03F $040 $050 $070 Data (144 digits) $100 Data (464 digits × 2) V = 0 (bank 0) V = 1 (bank 1) 0 1 2 3 4 5 6 7 8 9 10 11 $2CF 12 13 14 Interrupt control bits area Port mode register A Serial mode register $3BF 959 960 $3C0 Stack (64 digits) $3FF 1023 16 17 18 19 20 W W Serial data register lower (SRL) R/W Serial data register upper (SRU) R/W Timer mode register A (TMA) W Timer mode re
HD404818 Series Bit 3 Bit 2 Bit 1 Bit 0 0 IM0 (IM of INT0 ) IF0 (IF of INT0 ) RSP (Reset SP bit) 1 IMTA (IM of timer A) IFTA (IF of timer A) IM1 (IM of INT1 ) IF1 (IF of INT1 ) $001 2 IMTC (IM of timer C) IFTC (IF of timer C) IMTB (IM of timer B) IFTB (IF of timer B) $002 3 Not used Not used IMS (IM of serial) IFS (IF of serial) $003 32 DTON Direct transfer on flag Not used WDON (Watchdog on flag) LSON (Low speed on flag) $020 IE (Interrupt enable flag) $000 $021 Not used $0
HD404818 Series Memory registers 64 65 66 67 68 69 MR (0) MR (1) $040 MR (2) MR (3) $042 MR (4) $044 $045 Stack area 960 $041 $043 Level 16 Level 15 Level 14 Level 13 70 $046 Level 11 Level 10 71 MR (7) $047 Level 9 72 MR (8) MR (9) $048 Level 8 73 $049 74 MR (10) $04A 75 $04B 76 MR (11) MR (12) Level 7 Level 6 Level 5 $04C Level 4 77 MR (13) $04D Level 3 78 MR (14) MR (15) $04E Level 2 Level 1 $04F 1023 PC13 to PC0 : Program counter ST: Status flag CA: Carry flag
HD404818 Series Functional Description Registers and Flags The MCU provides ten registers and two flags for CPU operations. They are illustrated in figure 5 and described in the following paragraphs.
HD404818 Series V Register (V): The V register, available for RAM address expansion, selects the bank of locations $100– $2CF on the RAM address (464 digits) depending on its value. Therefore, when accessing locations $100– $2CF on the RAM address, specify the value of the V register (V = $0: bank 0; V = $1: bank 1). Locations $000–$0FF and $300–$3FF can be accessed independently of the V register. The V register is located at $03F of the RAM address area.
HD404818 Series Reset Setting the RESET pin high resets the MCU. At power-on or when cancelling the stop mode for the oscillator, apply the reset input for at least t RC for the oscillator to stabilize. In all other cases, at least two instruction cycles of reset input are required for the MCU reset. Table 1 shows the components initialized by MCU reset, and each of its status.
HD404818 Series Table 1 Initial Values after MCU Reset (cont) Items LCD Bit register Miscellaneous register Initial Value Contents LCD control register (LCR) 000 Refer to description of LCD Control Register LCD mode register (LMR) 0000 Refer to description of LCD Duty/Clock Control Low speed on flag (LSON) 0 Refer to description of Low-Power Dissipation Mode Watchdog timer on flag (WDON) 0 Refer to description of Timer C Direct transfer on flag (DTON) 0 Refer to description of Low-Power Di
HD404818 Series Interrupts Six interrupt sources are available on the MCU: external requests (INT0, INT1), timer/counters (timers A, B, and C), and the serial interface. For each source, an interrupt request flag (IF), interrupt mask (IM), and interrupt vector addresses are provided to control and maintain the interrupt request. The interrupt enable flag (IE) is also used to control interrupt operations.
HD404818 Series $ 000,0 Sequence control • Push PC/CA/ST • Reset IE • Jump to vector address IE $ 000,2 IF0 $ 000,3 IM0 Vector address Priority control logic $ 001,0 IF1 $ 001,1 IM1 $ 001,2 IFTA $ 001,3 IMTA $ 002,0 IFTB $ 002,1 IMTB $ 002,2 IFTC $ 002,3 IMTC $ 003,0 IFS $ 003,1 IMS Note: $m, n is RAM address $m, bit number n.
HD404818 Series Table 3 Interrupt Conditions Interrupt Source Interrupt Control Bit INT0 INT1 Timer A Timer B Timer C Serial IE 1 1 1 1 1 1 IF0 • IM0 1 0 0 0 0 0 IF1 • IM1 * 1 0 0 0 0 IFTA • IMTA * * 1 0 0 0 IFTB • IMTB * * * 1 0 0 IFTC • IMTC * * * * 1 0 IFS • IMS * * * * * 1 Note: *Don’t care. Figure 7 shows the interrupt processing sequence, and figure 8 shows the interrupt processing flowchart.
HD404818 Series Power on RESET = 1 ? Yes No Interrupt request ? Yes No No IE = 1? Yes Reset MCU Accept interrupt Execute instruction IE ←0 Stack ← (PC) Stack ← (CA) Stack ← (ST) PC ←(PC) + 1 PC← $0002 Yes INT0 interrupt ? No PC← $0004 Yes INT1 interrupt ? No PC← $0006 Yes Timer A interrupt ? No PC← $0008 Yes Timer B interrupt ? No PC ← $000A Yes Timer C interrupt ? No PC ← $000C Figure 8 Interrupt Processing Flowchart 22 (serial interrupt)
HD404818 Series Interrupt Enable Flag (IE: $000, Bit 0): The interrupt enable flag enables/disables interrupt requests (table 4). It is reset by an interrupt and set by the RTNI instruction. Table 4 Interrupt Enable Flag IE Interrupt Enabled/Disabled 0 Disabled 1 Enabled External Interrupts (INT0, INT1): The external interrupt request inputs (INT0, INT1) can be selected by port mode register A (PMRA: $004).
HD404818 Series Table 7 Timer A Interrupt Request Flag IFTA Interrupt Request 0 No 1 Yes Timer A Interrupt Mask (IMTA: $001, Bit 3): The timer A interrupt mask prevents an interrupt request from being generated by the timer A interrupt request flag (table 8). Table 8 Timer A Interrupt Mask IMTA Interrupt Request 0 Enabled 1 Disabled (masked) Timer B Interrupt Request Flag (IFTB: $002, Bit 0): The timer B interrupt request flag is set by the overflow output of timer B (table 9).
HD404818 Series Timer C Interrupt Mask (IMTC: $002, Bit 3): The timer C interrupt mask prevents the interrupt from being generated by the timer C interrupt request flag (table 12). Table 12 Timer C Interrupt Mask IMTC Interrupt Request 0 Enabled 1 Disabled (masked) Serial Interrupt Request Flag (IFS: $003, Bit 0): The serial interrupt request flag is set when the octal counter counts eight transmit clock signals, or when data transfer is discontinued by resetting the octal counter (table 13).
HD404818 Series Operating Modes The MCU has five operating modes that are specified by how the clock is used. The functions available in each mode are listed in table 15, and operations are shown in table 16. Transitions between operating modes are shown in figure 9. Table 16 provides additional information for table 26.
HD404818 Series Table 16 Operations in Low-Power Dissipation Modes Function Stop Mode Watch Mode Standby Mode Subactive Mode*2 CPU Reset Retained Retained OP RAM Retained Retained Retained OP Timer A Reset OP OP OP Timer B Reset Stopped OP OP Timer C Reset Stopped OP OP Stopped* OP OP OP OP OP Retained Retained OP Serial interface Reset LCD Reset 3 1 I/O Reset* Notes: OP indicates operating. 1. Output pins are at high impedance. 2.
HD404818 Series Reset Standby mode Active mode Stop mode (TMA3 = 0) f OSC : fX: ø CPU: ø CLK: ø PER: Operating Operating Stopped f cyc f cyc SBY (standby) Interrupt Timers A, B, C Serial, INT0 , INT 1 f OSC : fX: ø CPU: ø CLK: ø PER: (TMA3 = 0) Operating Operating f cyc f cyc f cyc STOP f OSC : fX: ø CPU: ø CLK: ø PER: Stopped Operating Stopped Stopped Stopped Watch mode (TMA3 = 1) f OSC : fX: ø CPU: ø CLK: ø PER: f OSC : fX: f cyc : f SUB : ø CPU : ø CLK : ø PER : LSON: DTON: Operating Ope
HD404818 Series the next instruction after the SBY instruction. If the interrupt enable flag is 1, that interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. A flowchart of operation in standby mode is shown in figure 10.
, HD404818 Series Stop Mode: The MCU enters stop mode if the STOP instruction is executed in active mode when TMA3 = 0. In this mode, the system oscillator stops, which stops all MCU functions as well. Stop mode is terminated by a RESET input as shown in figure 11. RESET must be high for at least one tRC to stabilize oscillation (refer to the AC Characteristics section).
HD404818 Series Oscillation stabilization period Active mode Watch mode Active mode Interrupt strobe INT0 Interrupt request generation T (During the transition from watch mode to active mode only) T tRC TX T: Interrupt frame length tRC: Oscillation stabilization period Figure 12 Interrupt Frame Subactive Mode: The CPU operates with a clock generated by the X1 and X2 oscillation circuits. Functions that can operate in subactive mode are listed in table 16.
HD404818 Series MIS: $00C MIS2 MIS MIS1 MIS0 T *1 t RC 1 Bit 0 Bit 0 0 0.24414 ms 0 1 1 0 15.625 ms 62.5 ms 1 1 t RC selection Refer to table 20 *1 0.12207 ms 0.24414 ms * 2 7.8125 ms 31.25 ms Not used Oscillation circuit condition External clock input Ceramic or crystal oscillator — Notes: 1. The value of t RC applies only when using a 32.768-kHz oscillator. 2. Only direct transfer.
HD404818 Series The low-power mode operation sequence is shown in figure 17. With the IE flag cleared and an interrupt flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY instruction, make sure all interrupt flags are cleared or all interrupts are masked.
HD404818 Series MCU operation cycle IF = 1 ? No Instruction execution Yes SBY/STOP instruction ? Yes No IM = 0 and IE = 1 ? Yes IE ← 0 Stack ← (PC), (CA), (ST) No Low-power mode operation cycle IF: IM: IE: PC: CA: ST: PC ← next location PC ← vector address Interrupt request flag Interrupt mask Interrupt enable flag Program counter Carry flag Status flag Figure 16 MCU Operating Sequence (MCU operation cycle) 34
HD404818 Series Low-power mode operation cycle IF = 1 and IM = 0 ? No Yes Standby/watch mode No Stop mode IF = 1 and IM = 0 ? Yes Hardware NOP execution Hardware NOP execution PC ← next Iocation PC ← next Iocation Instruction execution MCU operation cycle For specific IF and IM, see figure 10, MCU Operating Flowchart Figure 17 MCU Operating Sequence (low-power mode operation) Notes on Use: • In subactive mode, a timer A interrupt request or an external interrupt request (INT 0) occurs in sync
HD404818 Series • When the MCU is in watch mode or subactive mode, if the high level period before the falling edge of INT 0 is shorter than the interrupt frame, INT 0 is not be detected. Also, if the low level period after the falling edge of INT 0 is shorter than the interrupt frame, INT 0 is not be detected. Edge detection is shown in figure 18. The level of the INT0 signal is sampled by a sampling clock. When this sampled value changes to low from high, a falling edge is detected.
HD404818 Series Internal Oscillator Circuit , ' & % $ ./0'()!" +$ *# , Figure 20 shows the block diagram of the internal oscillator circuit. A ceramic oscillator can be connected to OSC 1 and OSC2. A 32.768-kHz crystal oscillator can be connected to X1 and X2. External clock operation is available for the system oscillator.
HD404818 Series Table 18 Examples of Oscillator Circuits Circuit Configuration Circuit Constants External clock operation Oscillator OSC 1 Open OSC 2 Ceramic oscillator C1 OSC1 Ceramic Rf OSC2 HD404812, HD404814, HD404816, HD404818, HD4074818 Ceramic oscillator: CSA4.
HD404818 Series Table 18 Examples of Oscillator Circuits (cont) Circuit Configuration Circuit Constants Crystal: 32.768 kHz: MX38T (Nippon Denpa Kogyo) C1: = 20 pF ± 20% C2: = 20 pF ± 20% RS: = 14 kΩ C0: = 1.5 pF Crystal oscillator C1 X1 Crystal X2 C2 GND L CS RS C0 Notes: 1. The circuit parameters above are recommended by the crystal or ceramic oscillator manufacturer. The circuit parameters are affected by the crystal or ceramic oscillator and floating capacitance when designing the board.
HD404818 Series Input/Output The MCU provides 26 I/O pins and 4 input-only pins including 10 high-current pins (15 mA max.). Twenty-six I/O pins contain programmable pull-up MOS. When each I/O pin is used as an input, the data control register (DCR) controls the output buffer. Table 19 shows the I/O pin circuit types. The configuration of the I/O buffers is shown in table 19.
HD404818 Series Table 19 I/O Pin Circuit Types I/O Pins I/O common pins (wint pull-up MOS) Circuit Pin Name VCC Pull-up control signal VCC DCR Output data PDR D0-D9 R0 0-R03 R1 0-R13 R2 0-R23 R3 0-R33 Input data Input control signal SCK VCC Pull-up control signal VCC DCR Output data SCK (internal) SCK Output pins (with pull-up MOS) VCC Pull-up control signal VCC DCR Output data Input pins SO or TIMO VCC PDR Pull-up control signal Input data Input control signal Input control VCref
HD404818 Series D Port: Consists of ten 1-bit I/O ports and four input ports. Pins D0 to D9 are high-current I/O pins (15 mA max.). The sum of the current for all D-port pins is up to 100 mA. D port can be set/reset by the SED/RED and SEDD/REDD instructions, and can be tested by the TD/TDD instruction. Output data is stored in the port data register. The output buffer for port D can be turned on/off by the D-port data control registers (DCRB, DCRC, DCRD). The DCR is located in the memory address area.
HD404818 Series Pin Internal bus MPX Comparator + – VC ref Mode register Figure 22 Configuration of D12 and D13 43
HD404818 Series SMR (serial mode register) ADR: $005 3 2 1 0 R0 0 /SCK pin mode selection PMRA (port mode register A) ADR: $004 3 2 1 0 R0 2 R01 R3 2 R3 3 /SO pin mode selection /SI pin mode selection /INT0 pin mode selection /INT1 pin mode selection PMRB (port mode register B) ADR: $012 3 2 1 0 D12 /COMP0 pin mode selection D13 /COMP1 pin mode selection R3 1 /TIMO pin mode selection Pull-up MOS on/off selection SMR Bit 3 Port select 0 R0 0 1 SCK Port select PMRA Port select PMRA Bit
HD404818 Series Table 20 Input/Output by Program Control PMRB Bit 3 0 1 DCR 0 PDR 0 1 0 1 0 1 0 1 PMOS (A) — — — On — — — On NMOS (B) — — On — — — On — Pull-up MOS — — — — — On — On 1 0 1 Notes: — indicates off status. 1. Combine the values of the above mode registers (PMRB3, DCR, and PDR) to select the input/output for PMOS (A), NMOS (B), and the pull-up MOS, individually. The DCR and PDR control each pin. Also, PMRB3 controls the on/off of all pull-up MOSs. 2.
HD404818 Series VCC PMRB3 VCC Pull-up MOS PMOS (A) DCR NMOS (B) PDR Input data Input control signal Figure 24 Configuration of the Input/Output Buffer 46
HD404818 Series Timers The MCU provides prescalers S and W (each with a different input clock source), and three timer/ counters (timers A, B, and C). Figures 25, 26 and 27 show their diagrams. Prescaler S: The input to prescaler S is the system clock signal. The prescaler is initialized to $000 by MCU reset, and starts to count up with the system clock signal as soon as the RESET input goes low. The prescaler keeps counting up except at MCU reset and in the stop and watch modes.
HD404818 Series 1/4 1/2 Timer A interrupt request flag (IFTA) (tsubcyc) Prescaler W (PSW) fSUB ÷2 ÷8 ÷ 16 ÷ 32 32.
HD404818 Series Timer B Operation: Timer mode register B (TMB: $009) selects the auto-reload function, input clock source, and prescaler divide ratio for timer B. When an external event input is used as an input clock signal to timer B, select R33/INT1 as INT1 by port mode register A (PMRA: $004) to prevent an external interrupt request from occurring (figure 26) Timer B is initialized according to the data written into timer load register B by software. Timer B counts up at every clock input signal.
HD404818 Series according to the value of timer load register C. If it is not selected, timer C goes to $00. The timer C interrupt request flag (IFTC: $002, bit 2) will be set as this overflow is output. Timer C is also available as a watchdog timer for detecting runaway programs. MCU reset occurs when the watchdog on flag (WDON) is 1 and the counter overflow output is generated by a runaway program. If timer C stops, the watchdog timer function also stops. In the standby mode, this function is enabled.
HD404818 Series T × (TCR + 1) TMC3 = 0 T T × 256 TMC3 = 1 T × (256 – TCR) Input clock period to counter (see table 23) T: TCR: The value of the timer load register Note: When TCR = $FF, this waveform is always fixed low.
HD404818 Series Registers for Timers Timer Mode Register A (TMA: $008): Timer mode register A is a 4-bit write-only register which controls the timer A operation as table 21 shows. Timer mode register A is initialized to $0 at MCU reset. Timer Mode Register B (TMB: $009): Timer mode register B (TMB) is a 4-bit write-only register which selects the auto-reload function, the prescaler divide ratio, and the source of the clock input signal, as shown in table 22.
HD404818 Series 5. The division ratio must not be modified during time base mode operation, otherwise an overflow cycle error will occur. Timer Mode Register C (TMC: $00D): Timer mode register C is a 4-bit write-only register which selects the auto-reload function, input clock source, and prescaler divide ratio, as table 23 shows. Timer mode register C is initialized to $0 at MCU reset. The contents of timer mode register C will change in the second instruction cycle after a write instruction to TMC.
HD404818 Series Table 23 Timer Mode Register C TMC3 Auto-Reload Function 0 No 1 Yes TMC2 TMC1 TMC0 Prescaler Divide Ratio, Clock Input Source 0 0 0 ÷ 2048 0 0 1 ÷ 1024 0 1 0 ÷ 512 0 1 1 ÷ 128 1 0 0 ÷ 32 1 0 1 ÷8 1 1 0 ÷4 1 1 1 ÷2 Notes on Use When using the timer output as variable duty-cycle pulse (PWM) output, note the following point.
HD404818 Series Table 24 PWM Output Following Update of Timer load Register PWM Output Mode Timer load Register is Updated during High PWM Output Timer load register updated to value N Free running Timer load Register is Updated during Low PWM Output Timer load register updated to value N Interrupt request T × (255 – N) T × (N + 1) Interrupt request T × (N' + 1) T × (255 – N) Timer load register updated to value N Reload T Interrupt request T × (255 – N) T Timer load register updated to value
HD404818 Series Serial Interface The serial interface transmits/receives 8-bit data serially. It consists of the serial data register, the serial mode register, port mode register A, the octal counter, and the selector (figure 29). Pin R00/SCK and the transmit clock signal are controlled by the serial mode register. The data of the serial data register can be written and read by software. The data in the serial data register can be shifted synchronously with the transmit clock signal.
HD404818 Series Selection and Change of the Operation Mode: Table 25 shows the serial interface operation modes which are determined by a combination of the value in the port mode register and in the serial mode register. Initialize the serial interface by writing to the serial mode register to change the operation mode of the serial interface.
HD404818 Series STS waiting state on cti SM tru ST S ins to rite r te Transmit clock Transmit clock wait state (Octal counter = 000) ite wr ) 1 R s ← ck SM S clo (IF it m ns ) ra ← 1 lt na IFS ( in W 8 R Octal counter = 000 transmit clock disable 8 external transmit clocks STS instruction Transfer state (Octal counter ≠ 000) (IFS ← 1) Figure 30 Serial Interface Operation States Example of Transmit Clock Error Detection: The serial interface malfunctions when the transmit clock is disturbed
HD404818 Series Transmission finished (IFS ← 1) Disable interrupt IFS ← 0 Write to SMR IFS = 1 ? Yes Transmit clock error processing No Normal end Figure 31 Transmit Clock Error Detection 59
HD404818 Series Registers for Serial Interface Serial Mode Register (SMR: $005): The 4-bit write-only serial mode register controls the R00/SCK, prescaler divide ratio, and transmit clock source (table 26, figure 32). A write signal to the serial mode register controls the internal state of the serial interface. A write signal to the serial mode register stops the serial data register and octal counter from applying the transmit clock, and it also resets the octal counter to $0 simultaneously.
HD404818 Series PMRA: $004 SMR: $005 PMRA3 PMRA2 PMRA1 PMRA0 SMR3 SMR2 SMR1 SMR0 Transmit clock selection R00/SCK pin mode selection R02/SO pin mode selection R01/SI pin mode selection Figure 32 Configurations and Functions of the Mode Registers Transmit clock 1 Serial output data 2 3 4 5 6 LSB 7 8 MSB Serial input data latch timing Figure 33 Serial Interface I/O Timing 61
HD404818 Series LCD Controller/Driver The MCU contains four common signal pins, the controller, and the driver. The controller and the driver drive 32 segment signal pins. The controller consists of display data RAM, the LCD control register (LCR), and the LCD duty-cycle/clock control register (LMR) (figure 34). Four programmable duty cycles and LCD clocks are available. Since the MCU contains a dual port RAM, display data can be transferred to segment signal pins automatically without program control.
HD404818 Series Bit 3 Bit 2 Bit 1 Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 80 SEG1 SEG1 SEG1 SEG1 $050 96 SEG17 SEG17 SEG17 SEG17 $060 81 SEG2 SEG2 SEG2 SEG2 $051 97 SEG18 SEG18 SEG18 SEG18 $061 82 SEG3 SEG3 SEG3 SEG3 $052 98 SEG19 SEG19 SEG19 SEG19 $062 83 SEG4 SEG4 SEG4 SEG4 $053 99 SEG20 SEG20 SEG20 SEG20 $063 84 SEG5 SEG5 SEG5 SEG5 $054 100 SEG21 SEG21 SEG21 SEG21 $064 85 SEG6 SEG6 SEG6 SEG6 $055 101 SEG22 SEG22 SEG22 SEG22 $065 86 SE
HD404818 Series Table 27 LCD Control Register LCR BIT 2 Watch Mode/ Subactive Mode LCR Display BIT 1 Power Switch On/Off LCR BIT 0 Blank/ Display 0 Off 0 Off 0 Blank 1 On 1 On 1 Display Note: With the LCD in watch mode, use the divider output of the 32-kHz oscillator as an LCD clock and set LCR bit 2 to 1. When the system oscillator divider output is used as an LCD clock, set LCR bit 2 to 0.
HD404818 Series Table 29 LCD Frame Frequency LMR Static Bit 3 Bit 2 Bit 3 Bit 2 Bit 3 Bit 2 Bit 3 Bit 2 Instruction cycle time 0 0 0 1 1 0 1 1 CL0 CL1 CL2 CL3* 10 µs 512 Hz 390.6 Hz 48.8 Hz 24.4 Hz/64 Hz 1 µs 512 Hz 3906 Hz 488Hz 244 Hz/64 Hz LMR 1/2 Duty Cycle Bit 3 Bit 2 Bit 3 Bit 2 Bit 3 Bit 2 Bit 3 Bit 2 Instruction cycle time 0 0 0 1 1 0 1 1 CL0 CL1 CL2 CL3* 10 µs 256 Hz 195.3 Hz 24.4 Hz 12.
HD404818 Series Large LCD Panel Driving and Driving Voltage (VLCD ): When using a large LCD panel, lower the dividing resistance by attaching external resistors in parallel with the internal dividing resistors (figure 37). Since the liquid crystal display board is of a matrix configuration, the path of the charge/discharge current through the load capacitors is very complicated.
HD404818 Series VCC (V 1 ) VCC (V1 ) R R C V2 V2 R R V3 C V3 C R C = 0.1 to 0.3 µF R GND GND VCC VCC VLCD COM1 . V1 SEG1 V2 to V3 SEG32 GND 4-digit LCD with signal 32 Static drive VCC VCC VLCD VLCD 2 . V1 SEG1 V2 to V3 SEG32 GND VCC VCC COM1 COM2 8-digit LCD 32 1/2 duty, 1/2 bias drive COM1 3 to . COM3 V1 V2 SEG1 to V3 GND SEG32 10-digit LCD with signal 32 1/3 duty, 1/3 bias drive VCC VCC VCC ≥ V LCD ≥ GND VLCD COM1 to COM4 4 V1 V2 SEG1 to V3 GND SEG32 .
HD404818 Series Pin Description in PROM Mode The HD4074818 and HD407L4818 are ZTAT microcomputers incorporating a PROM. In the PROM mode, the MCU does not operate and the HD4074818 and HD407L4818 can program the on-chip PROM.
HD404818 Series MCU Mode PROM Mode Pin Number MCU Mode PROM Mode FP-80A FP-80B TFP-80 Pin Name I/O Pin Name Pin Number FP80B FP-80A TFP-80 Pin Name I/O Pin Name 55 53 SEG23 O 68 66 COM4 56 54 SEG24 O 69 67 V1 57 55 SEG25 O 70 68 V2 58 56 SEG26 O 71 69 V3 59 57 SEG27 O 72 70 NUMO 60 58 SEG28 O 73 71 NUMO 61 59 SEG29 O 74 72 NUMG VCC 62 60 SEG30 O 75 73 VCC VCC 63 61 SEG31 O 76 74 OSC 1 I 64 62 SEG32 O 77 75 OSC 2 O 65 63 CO
HD404818 Series Programmable ROM Operation The MCU on-chip PROM is programmed in PROM mode. PROM mode is set by pulling TEST, M0, and M1 low, and RESET high, as shown in figure 38. In PROM mode, the MCU does not operate. It can be programmed like a standard 27256 EPROM using a standard PROM programmer and an 80-to-28-pin socket adapter. Table 31 lists the recommended PROM programmers and socket adapters.
HD404818 Series Table 31 PROM Programmers and Socket Adapters PROM Programmer Socket Adapter Manufacturer Type Name Manufacturer Type Name Package Type DATA I/O 121B 29B Hitachi HS460ESF01H FP-80B HS460ESH01H FP-80A HS461EST01H TFP-80 HS460ESF01H FP-80B HS460ESH01H FP-80A HS461EST01H TFP-80 AVAL Corp.
HD404818 Series Addressing Modes RAM Addressing Modes As shown in figure 39, the MCU has three RAM addressing modes: register indirect addressing, direct addressing, and memory register addressing. Register Indirect Addressing Mode: The W register, X register, and Y register contents (10 bits total) are used as the RAM address. Direct Addressing Mode: A direct addressing instruction consists of two words, with the word (10 bits) following the opcode used as the RAM address.
HD404818 Series The P instruction has no effect on the program counter.
HD404818 Series Instruction 1st word [JMPL] [BRL] [CALL] Opcode p3 Program counter Instruction 2nd word p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Direct Addressing Instruction [BR] Program counter Opcode b7 b6 b5 b4 b3 b2 b1 b0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Current Page Addressing Instruction [CAL] 0 Program counter 0 0 a5 Opcode 0 0 0 0 a4 a3 a2 a1 a0 0 PC13
HD404818 Series 256 (n – 1) + 255 BR AAA 256n AAA NOP BR AAA BR BBB 256n + 254 256n + 255 256 (n + 1) BBB NOP Figure 41 Page Boundary between BR Instruction and Branch Destination 75
HD404818 Series Instruction [P] Opcode P3 P2 P1 P0 B register B3 0 B2 B1 Accumulator B0 A3 A2 A1 A0 0 Referred ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0 Address Designation ROM data RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Accumulator, B register ROM data B3 B2 B1 B0 A3 A A1 A 0 If RO 8 = 1 RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Output registers R1, R2 R23 R22 R21 R20 R13 R12 R11 R10 Pattern Figure 42 P Instruction 76 2 If RO 9 = 1
HD404818 Series Absolute Maximum Ratings HD404812, HD404814, HD404816, HD404818, and HD4074818 Absolute Maximum Ratings Item Symbol Value Unit Supply voltage VCC –0.3 to +7.0 V Programming voltage VPP –0.3 to +14.0 V Pin voltage VT –0.3 to VCC +0.
HD404818 Series HD40L4812, HD40L4814, HD40L4816, HD40L4818, and HD407L4818 Absolute Maximum Ratings Item Symbol Value Unit Supply voltage VCC –0.3 to +7.0 V Programming voltage VPP –0.3 to +14.0 V Pin voltage VT –0.3 to VCC + 0.
HD404818 Series Electrical Characteristics for Standard-Voltage HD404812, HD404814, HD404816, HD404818, and HD4074818 Electrical Characteristics DC Characteristics (HD404812, HD404814, HD404816, HD404818: VCC = 4 to 6 V; HD4074818: VCC = 4 to 5.5 V; GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pin Min Input high voltage VIH RESET, SCK, INT0, SI, INT1 Input low voltage VIL Max Unit 0.8V CC VCC + 0.3 V OSC 1 VCC – 0.5 VCC + 0.3 V RESET, SCK, INT0, SI, INT1 –0.
HD404818 Series Item Symbol Pin Min Typ Max Unit Test Condition I WTC1 Current dissipation in watch mode (1) VCC 10 20 µA VCC = 5 V, LCD: Off I WTC2 Current dissipation in watch mode (2) VCC 25 50 µA VCC = 5 V, LCD: On Current I STOP dissipation in stop mode VCC 1 10 µA VCC = 5 V, Notes: 1. Excluding output buffer current. 2. The MCU is in the reset state. Input/output current does not flow. • MCU in reset state • RESET, TEST: V CC 3.
HD404818 Series Input/Output Characteristics for Standard Pins (HD404812, HD404814, HD404816, HD404818: V CC = 4 to 6 V; HD4074818: V CC = 4 to 5.5 V; GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pin Min Input high voltage VIH D10–D 13 , R0– R3 Input low voltage VIL Output high voltage Max Unit 0.7V CC VCC + 0.3 V D10–D 13 , R0–R3 –0.3 0.3V CC V VOH R0–R3 VCC – 1.
HD404818 Series Input/Output Characteristics for High-Current Pins (HD404812, HD404814, HD404816, HD404818: VCC = 4 to 6 V; HD4074818: VCC = 4 to 5.5 V; GND = 0V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pin Min Input high voltage VIH D0–D 9 Input low voltage VIL Output high voltage Max Unit 0.7V CC VCC + 0.3 V D0–D 9 –0.3 0.3V CC V VOH D0–D 9 VCC – 1.
HD404818 Series AC Characteristics (HD404812, HD404814, HD404816, HD404818: VCC = 4 to 6 V; HD4074818: VCC = 4 to 5.5 V; GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pin Min Typ Max Unit Oscillation frequency f OSC OSC 1, OSC 2 1.6 4.0 4.2 MHz X1, X2 Oscillation frequency f OSC Instruction cycle time t cyc Oscillator stabilization time t RC OSC 1, OSC 2 (without 32 kHz) 32.768 4.0 4.2 MHz 0.95 1 2.5 µs 0.
HD404818 Series Item Symbol Pin Min RESET high width t RSTH RESET 2 Input capacitance Cin D10 All pins except D10 RESET fall time t RSTf Analog comparator stabilization time t CSTB D12, D13 Typ Max Unit Test Condition Notes t cyc 5 15 pF f = 1 MHz, Vin = 0 V 8 90 pF f = 1 MHz, Vin = 0 V 9 15 pF f = 1 MHz, Vin = 0 V 20 ms 5 2 t cyc 7 Notes: 1. The oscillator stabilization time is the period up until the time the oscillator stabilizes after V CC reaches 4.
HD404818 Series Serial Interface Timing Characteristics During Transmit Clock Output (HD404812, HD404814, HD404816, HD404818: V CC = 4 to 6 V; HD4074818: V CC = 4 to 5.5 V; GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Transmit clock cycle time t Scyc Pin SCK Min Typ Max Unit Test Condition Notes 1 t cyc / t subcyc 1, 2, 4 0.
HD404818 Series 1/fCP VCC – 0.5 V 0.5 V OSC1 tCPH tCPr tCPL tCPf Figure 43 Oscillator Timing 0.8VCC 0.2VCC INT0, INT1 tIH tIL Figure 44 Interrupt Timing 0.8VCC 0.2VCC RESET tRSTH tRSTf Figure 45 Reset Timing t Scyc t SCKf SCK VCC – 2.0 V (0.8VCC )* 0.8 V (0.2VCC)* t SCKr After 8 pulses are input t SCKH t SCKHD t SCKL t DSO SO VCC – 2.0 V 0.8 V t SSI SI t HSI 0.8V CC 0.2VCC Note: * VCC – 2.0 V and 0.8 V are the threshold voltages for transmit clock output. 0.8V CC and 0.
HD404818 Series VCC R L = 2.
HD404818 Series Electrical Characteristics for Low-Voltage Versions HD40L4812, HD40L4814, HD40L4816, HD40L4818, and HD407L4818 Electrical Characteristics DC Characteristics (HD40L4812, HD40L4814, HD40L4816, HD40L4818: VC C = 2.7 to 6 V; HD407L4818: VCC = 3 to 5.5 V; GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pin Min Input high voltage VIH RESET, SCK, INT0, SI, INT1 Input low voltage VIL Max Unit 0.9V CC VCC + 0.3 V OSC 1 VCC – 0.3 VCC + 0.
HD404818 Series Item Symbol Pin Min Typ Max Unit Test Condition I WTC1 Current dissipation in watch mode (1) VCC 5 15 µA VCC = 3 V, LCD: Off I WTC2 Current dissipation in watch mode (2) VCC 15 35 µA VCC = 3 V, LCD: On Current I STOP dissipation in stop mode VCC 1 10 µA VCC = 3 V, Without 32-kHz oscillator Notes Notes: 1. Excluding output buffer current. 2. The MCU is in the reset state. Input/output current does not flow. • MCU in reset state • RESET, TEST: V CC 3.
HD404818 Series Input/Output Characteristics for Standard Pins (HD40L4812, HD40L4814, HD40L4816, HD40L4818: VCC = 2.7 to 6 V; HD407L4818: VCC = 3 to 5.5 V; GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pin Min Input high voltage VIH D10–D 13 , R0–R3 Input low voltage VIL Output high voltage Max Unit 0.7V CC VCC + 0.3 V D10–D 13 , R0–R3 –0.3 0.3V CC V VOH R0–R3 VCC –1.
HD404818 Series Input/Output Characteristics for High-Current Pins (HD40L4812, HD40L4814, HD40L4816, HD40L4818: VCC = 2.7 to 6 V; HD407L4818: VCC = 3 to 5.5 V; GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pin Min Input high voltage VIH D0–D 9 Input low voltage VIL Output high voltage Max Unit 0.7V CC VCC + 0.3 V D0–D 9 –0.3 0.3V CC V VOH D0–D 9 VCC –1.
HD404818 Series AC Characteristics (HD40L4812, HD40L4814, HD40L4816, HD40L4818: VC C = 2.7 to 6 V; HD407L4818: VCC = 3 to 5.5 V; GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Oscillation frequency f OSC OSC 1, OSC 2 250 800 900 kHz X1, X2 Instruction cycle time t cyc Oscillator stabilization time t RC 32.768 4.45 OSC 1, OSC 2 X1, X2 External clock frequency f CP 5 Test Condition Notes kHz 16 µs 7.5 ms f OSC = 400 kHz 1 7.
HD404818 Series 2. The oscillator stabilization time is the period from when VCC reaches 2.7 V (HD407L4818: VCC = 3.0 V) at power-on until the oscillator stabilizes. The time required to stabilize the oscillator (t RC) must be obtained. Since tRC depends on the ceramic oscillator’s circuit constant and stray capacitance, consult with the ceramic oscillator manufacturer. 3. See figure 48. 4. See figure 49. The unit t cyc is applied when the MCU is in standby mode or active mode. 5. See figure 50. 6.
HD404818 Series During Transmit Clock Input Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes Transmit clock cycle time t Scyc SCK 1 t cyc / t subcyc 1, 4 Transmit clock high and low widths t SCKH, t SCKL SCK 0.
HD404818 Series After 8 pulses are input t Scyc t SCKf SCK VCC – 1.0 V (0.9VCC ) * 0.4 V (0.1VCC) * t SCKr t SCKL t SCKH t SCKHD t DSO SO VCC – 1.0 V 0.4 V t HSI t SSI 0.9V CC 0.1VCC SI Note: * VCC – 1.0 V and 0.4 V are the threshold voltages for transmit clock output. 0.9VCC and 0.1VCC are the threshold voltages for transmit clock input. Figure 51 Timing of Serial Interface VCC R L = 2.
HD404818 Series Notes on ROM Out Please pay attention to the following items regarding ROM out. On ROM out, fill the ROM area indicated below with 1s to create the same data size as an 8-kword version (HD404818 and HD40L4818). An 8-kword data size is required to change ROM data to mask manufacturing data since the program used is for an 8-kword version. This limitation applies when using an EPROM or a data base.
HD404818 Series HD404812, HD404814, HD404816, HD404818, HD40L4812, HD40L4814, HD40L4816, HD40L4818 Option List Please check off the appropriate applications and enter the necessary information. HD404812 2-kword HD404814 HD404816 Department 4-kword ROM code name 6-kword LSI type number (Hitachi’s entry) Low-voltage operation HD40L4814 5-V operation / Name Low-voltage operation HD40L4812 5-V operation / Customer 1.
HD404818 Series Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice.