Emulation Pod User's Manual

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(2) Separate Bus, With Wait, Accessing External Memory Area

Table 5.7 and Figure 5.7 show the bus timing in the memory expansion mode and the microprocessor

mode (with wait, accessing external memory area and using multiplex bus).

Table 5.7 Memory expansion mode and microprocessor mode (with wait, external memory area)

*1 Calculated by the following formula according to the frequency of BCLK.

Td (BCLK-AD)

Th (BCLK-AD)

Th (RD-AD)

Th (WR-AD)

Td (BCLK-CS)

Th (BCLK-CS)

Td (BCLK-ALE)

Th (BCLK-ALE)

Td (BCLK-RD)

Th (BCLK-RD)

Td (BCLK-WR)

Th (BCLK-WR)

Td (BCLK-DB)

Th (BCLK-DB)

Td (DB-WR)

Th (WR-DB)

Address output delay time

Address output hold time (BCLK standard)

Address output hold time (RD standard)

Address output hold time (WR standard)

Chip-select output delay time

Chip-select output hold time (BCLK standard)

ALE signal output delay time

ALE signal output hold time

RD signal output delay time

RD signal output hold time

WR signal output delay time

WR signal output hold time

Data output delay time (BCLK standard)

Data output hold time (BCLK standard)

Data output delay time (WR standard)

Data output hold time (WR standard)

Min.

-4

(*1)

Max.

Min. Max.

Actual MCU

[ns]

This product

[ns]

Symbol

Item

Td (DB-WR)=

f(BCLK)

-80 [ns]

See left