Datasheet

Appendix
Rev. 1.50 Sep. 18, 2007 Page 522 of 584
REJ09B0240-0150
Symbol Description
∧ Logical AND of the operands on both sides
∨ Logical OR of the operands on both sides
⊕ Logical exclusive OR of the operands on both sides
¬ NOT (logical complement)
( ), < > Contents of operand
↔
Changed according to execution result
* Undetermined (no guaranteed value)
0 Cleared to 0
1 Set to 1
— Not affected by execution of the instruction
∆ Varies depending on conditions, described in notes
Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers
(R0 to R7 and E0 to E7).