Datasheet

Section 1 Overview
Rev. 1.50 Sep. 18, 2007 Page 1 of 584
REJ09B0240-0150
Section 1 Overview
1.1 Features
• High-speed H8/300H central processing unit with an internal 16-bit architecture
Upward-compatible with H8/300 CPU on an object level
Sixteen 16-bit general registers
62 basic instructions
• Various peripheral functions
RTC (can be used as a free running counter)
Timer B1 (8-bit timer)
Timer V (8-bit timer)
Timer RC (16-bit timer)
Timer RD (16-bit timer)
14-bit PWM
Watchdog timer
SCI3 (Asynchronous or clock synchronous serial communication interface)
I
2
C bus interface 2 (conforms to the I
2
C bus interface format that is advocated by Philips
Electronics)
10-bit A/D converter
POR/LVD (Power-on reset and low-voltage detection circuit) (optional)
• On-chip memory
Model
Product
Classification
Standard
Version
On-Chip Power-
On Reset and
Low-Voltage
Detection Circuit
Version ROM RAM Remark
Flash memory version
(F-ZTAT
TM
version)
H8/36109F HD64F36109 HD64F36109G 128 kbytes 5 kbytes
Note: F-ZTAT
TM
is a trademark of Renesas Technology Corp.