Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 283 of 584
REJ09B0240-0150
Bit Bit Name
Initial
Value R/W Description
5 EB1 1 R/W Master Enable B1
0: FTIOB1 pin output is enabled according to the
TRDPMR, TRDFCR, and TRDIORA_1 settings
1: FTIOB1 pin output is disabled regardless of the
TRDPMR, TRDFCR, and TRDIORA_1 settings
(FTIOB1 pin is operated as an I/O port).
4 EA1 1 R/W Master Enable A1
0: FTIOA1 pin output is enabled according to the
TRDPMR, TRDFCR, and TRDIORA_1 settings
1: FTIOA1 pin output is disabled regardless of the
TRDPMR, TRDFCR, and TRDIORA_1 settings
(FTIOA1 pin is operated as an I/O port).
3 ED0 1 R/W Master Enable D0
0: FTIOD0 pin output is enabled according to the
TRDPMR, TRDFCR, and TRDIORC_0 settings
1: FTIOD0 pin output is disabled regardless of the
TRDPMR, TRDFCR, and TRDIORC_0 settings
(FTIOD0 pin is operated as an I/O port).
2 EC0 1 R/W Master Enable C0
0: FTIOC0 pin output is enabled according to the
TRDPMR, TRDFCR, and TRDIORC_0 settings
1: FTIOC0 pin output is disabled regardless of the
TRDPMR, TRDFCR, and TRDIORC_0 settings
(FTIOC0 pin is operated as an I/O port).
1 EB0 1 R/W Master Enable B0
0: FTIOB0 pin output is enabled according to the
TRDPMR, TRDFCR, and TRDIORA_0 settings
1: FTIOB0 pin output is disabled regardless of the
TRDPMR, TRDFCR, and TRDIORA_0 settings
(FTIOB0 pin is operated as an I/O port).
0 EA0 1 R/W Master Enable A0
0: FTIOA0 pin output is enabled according to the
TRDPMR, TRDFCR, and TRDIORA_0 settings
1: FTIOA0 pin output is disabled regardless of the
TRDPMR, TRDFCR, and TRDIORA_0 settings
(FTIOA0 pin is operated as an I/O port).