Datasheet

Section 13 Timer RC
Rev. 1.50 Sep. 18, 2007 Page 224 of 584
REJ09B0240-0150
13.3.2 Timer RC Control Register 1 (TRCCR1)
TRCCR1 specifies the source of the counter clock, clearing conditions, and initial output levels of
TRCCNT.
Bit Bit Name
Initial
Value
R/W Description
7 CCLR 0 R/W Counter Clear
The TRCCNT value is cleared by compare match A when
this bit is 1. When it is 0, TRCCNT functions as a free-
running counter.
6
5
4
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Clock Select 2 to 0
Select the source of the clock input to TRCCNT.
000: TRCCNT counts the internal clock φ
001: TRCCNT counts the internal clock φ/2
010: TRCCNT counts the internal clock φ/4
011: TRCCNT counts the internal clock φ/8
100: TRCCNT counts the internal clock φ/32
101: TRCCNT counts the rising edge of the external
event (FTCI)
110: TRCCNT counts the internal clock φ40M
111: Reserved (setting prohibited)
When the internal clock (φ) is selected, TRCCNT counts
the subclock in subactive or subsleep mode. *
Note: * When selecting the internal clock φ40M, the
on-chip oscillator should be in operation.
When switching the clock, the counter should
be halted.
3 TOD 0 R/W Timer Output Level Setting D
Sets the output value of the FTIOD pin until the first
compare match D is generated. In PWM mode, controls
the output polarity of the FTIOD pin.
0: Output value is 0*
1: Output value is 1*
2 TOC 0 R/W Timer Output Level Setting C
Sets the output value of the FTIOC pin until the first
compare match C is generated. In PWM mode, controls
the output polarity of the FTIOC pin.
0: Output value is 0*
1: Output value is 1*