Datasheet

Section 6 Power-Down Modes
Rev. 1.50 Sep. 18, 2007 Page 94 of 584
REJ09B0240-0150
6.1.3 System Control Register 3 (SYSCR3)
SYSCR3 controls waiting time in combination with SYSCR1.
Bit Bit Name
Initial
Value R/W Description
7 STS3 1 R/W Standby Timer Select 3
This bit selects the waiting time in combination with bits
STS2 to STS0 in SYSCR1.
The relationship between the register setting and
waiting time is shown in table 6.1.
6 to 0  All 1  Reserved
These bits are always read as 0.
6.1.4 Module Standby Control Register 1 (MSTCR1)
MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units.
Bit Bit Name
Initial
Value R/W Description
7  0  Reserved
This bit is always read as 0.
6 MSTIIC 0 R/W IIC2 Module Standby
IIC2 enters the standby mode when this bit is set to 1
5 MSTS3 0 R/W SCI3 Module Standby
SCI3 enters the standby mode when this bit is set to 1
4  0  Reserved
This bit is always read as 0.
3 MSTWD 0 R/W Watchdog Timer Module Standby
Watchdog timer enters the standby mode when this bit
is set to 1. When the on-chip oscillator is selected for
the watchdog timer clock, the watchdog timer operates
regardless of the setting of this bit
2  0  Reserved
This bit is always read as 0.