Datasheet

Rev. 2.00 Sep. 23, 2005 Page x of xxx
3.2.4 Interrupt Enable Register 2 (IENR2)...................................................................... 51
3.2.5 Interrupt Flag Register 1 (IRR1)............................................................................. 51
3.2.6 Interrupt Flag Register 2 (IRR2)............................................................................. 53
3.2.7 Wakeup Interrupt Flag Register (IWPR)................................................................ 53
3.3 Reset Exception Handling.................................................................................................... 55
3.4 Interrupt Exception Handling .............................................................................................. 55
3.4.1 External Interrupts .................................................................................................. 55
3.4.2 Internal Interrupts ................................................................................................... 57
3.4.3 Interrupt Handling Sequence .................................................................................. 57
3.4.4 Interrupt Response Time......................................................................................... 58
3.5 Usage Notes......................................................................................................................... 60
3.5.1 Interrupts after Reset............................................................................................... 60
3.5.2 Notes on Stack Area Use ........................................................................................ 60
3.5.3 Notes on Rewriting Port Mode Registers ............................................................... 60
Section 4 Address Break .....................................................................................61
4.1 Register Descriptions...........................................................................................................62
4.1.1 Address Break Control Register (ABRKCR) ......................................................... 62
4.1.2 Address Break Status Register (ABRKSR) ............................................................ 64
4.1.3 Break Address Registers (BARH, BARL).............................................................. 64
4.1.4 Break Data Registers (BDRH, BDRL) ................................................................... 64
4.2 Operation ............................................................................................................................. 65
Section 5 Clock Pulse Generators .......................................................................67
5.1 System Clock Generator...................................................................................................... 68
5.1.1 Connecting Crystal Resonator ................................................................................ 68
5.1.2 Connecting Ceramic Resonator .............................................................................. 69
5.1.3 External Clock Input Method ................................................................................. 69
5.2 Subclock Generator..............................................................................................................70
5.2.1 Connecting 32.768-kHz Crystal Resonator ............................................................ 70
5.2.2 Pin Connection when Not Using Subclock............................................................. 71
5.3 Prescalers............................................................................................................................. 71
5.3.1 Prescaler S .............................................................................................................. 71
5.3.2 Prescaler W............................................................................................................. 71
5.4 Usage Notes......................................................................................................................... 72
5.4.1 Note on Resonators................................................................................................. 72
5.4.2 Notes on Board Design........................................................................................... 72