Datasheet

Section 18 I
2
C Bus Interface 2 (IIC2)
Rev. 3.00 Mar. 15, 2006 Page 352 of 526
REJ09B0060-0300
18.3.5 I
2
C Bus Status Register (ICSR)
ICSR performs confirmation of interrupt request flags and status.
Bit Bit Name
Initial
Value R/W Description
7 TDRE 0 R/W Transmit Data Register Empty
[Setting conditions]
• When data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
• When TRS is set
• When a start condition (including re-transfer) has
been issued
• When transmit mode is entered from receive mode
in slave mode
[Clearing conditions]
• When 0 is written in TDRE after reading TDRE = 1
• When data is written to ICDRT with an instruction
6 TEND 0 R/W Transmit End
[Setting conditions]
• When the ninth clock of SCL rises with the I
2
C bus
format while the TDRE flag is 1
• When the final bit of transmit frame is sent with the
clock synchronous serial format
[Clearing conditions]
• When 0 is written in TEND after reading TEND = 1
• When data is written to ICDRT with an instruction
5 RDRF 0 R/W Receive Data Register Full
[Setting condition]
• When a receive data is transferred from ICDRS to
ICDRR
[Clearing conditions]
• When 0 is written in RDRF after reading RDRF = 1
• When ICDRR is read with an instruction