Datasheet

Rev. 3.00 Mar. 15, 2006 Page xxx of xxxii
Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is
Possible................................................................................................................... 98
Table 7.4 Reprogram Data Computation Table .................................................................... 102
Table 7.5 Additional-Program Data Computation Table...................................................... 102
Table 7.6 Programming Time............................................................................................... 102
Table 7.7 Flash Memory Operating States............................................................................ 107
Section 10 Realtime Clock (RTC)
Table 10.1 Pin Configuration.................................................................................................. 148
Table 10.2 Interrupt Sources................................................................................................... 159
Section 11 Timer B1
Table 11.1 Pin Configuration.................................................................................................. 161
Table 11.2 Timer B1 Operating Modes .................................................................................. 164
Section 12 Timer V
Table 12.1 Pin Configuration.................................................................................................. 167
Table 12.2 Clock Signals to Input to TCNTV and Counting Conditions ............................... 170
Section 13 Timer W
Table 13.1 Timer W Functions ............................................................................................... 182
Table 13.2 Pin Configuration.................................................................................................. 184
Section 14 Timer Z
Table 14.1 Timer Z Functions ................................................................................................ 214
Table 14.2 Pin Configuration.................................................................................................. 218
Table 14.3 Initial Output Level of FTIOB0 Pin...................................................................... 249
Table 14.4 Output Pins in Reset Synchronous PWM Mode................................................... 254
Table 14.5 Register Settings in Reset Synchronous PWM Mode........................................... 254
Table 14.6 Output Pins in Complementary PWM Mode........................................................ 258
Table 14.7 Register Settings in Complementary PWM Mode................................................ 258
Table 14.8 Register Combinations in Buffer Operation ......................................................... 268
Section 16 14-Bit PWM
Table 16.1 Pin Configuration.................................................................................................. 295
Section 17 Serial Communication Interface 3 (SCI3)
Table 17.1 Channel Configuration.......................................................................................... 300
Table 17.2 Pin Configuration.................................................................................................. 303
Table 17.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...... 310
Table 17.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ...... 312
Table 17.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3) ...... 314
Table 17.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 315