Datasheet

Rev. 3.00 Mar. 15, 2006 Page xxvii of xxxii
Figure 18.17 Sample Flowchart for Master Transmit Mode.......................................................369
Figure 18.18 Sample Flowchart for Master Receive Mode ........................................................ 370
Figure 18.19 Sample Flowchart for Slave Transmit Mode.........................................................371
Figure 18.20 Sample Flowchart for Slave Receive Mode .......................................................... 372
Figure 18.21 Timing of Bit Synchronous Circuit ....................................................................... 374
Section 19 A/D Converter
Figure 19.1 Block Diagram of A/D Converter ........................................................................... 378
Figure 19.2 A/D Conversion Timing.......................................................................................... 385
Figure 19.3 External Trigger Input Timing ................................................................................ 386
Figure 19.4 A/D Conversion Accuracy Definitions (1).............................................................. 388
Figure 19.4 A/D Conversion Accuracy Definitions (2).............................................................. 389
Figure 19.5 Analog Input Circuit Example................................................................................. 390
Section 20 Power-On Reset and Low-Voltage Detection Circuits (Optional)
Figure 20.1 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection
Circuit...................................................................................................................... 392
Figure 20.2 Operational Timing of Power-On Reset Circuit...................................................... 396
Figure 20.3 Operational Timing of LVDR Circuit ..................................................................... 398
Figure 20.4 Operational Timing of LVDI Circuit....................................................................... 399
Figure 20.5 Timing for Operation/Release of Low-Voltage Detection Circuit .......................... 400
Section 21 Power Supply Circuit
Figure 21.1 Power Supply Connection when Internal Step-Down Circuit is Used .................... 401
Figure 21.2 Power Supply Connection when Internal Step-Down Circuit is Not Used ............. 402
Section 23 Electrical Characteristics
Figure 23.1 System Clock Input Timing..................................................................................... 459
Figure 23.2 RES Low Width Timing.......................................................................................... 459
Figure 23.3 Input Timing............................................................................................................ 460
Figure 23.4 I
2
C Bus Interface Input/Output Timing ................................................................... 460
Figure 23.5 SCK3 Input Clock Timing.......................................................................................460
Figure 23.6 SCI Input/Output Timing in Clocked Synchronous Mode ...................................... 461
Figure 23.7 Output Load Circuit................................................................................................. 461
Appendix
Figure B.1 Port 1 Block Diagram (P17) ..................................................................................... 493
Figure B.2 Port 1 Block Diagram (P14, P16) ............................................................................. 494
Figure B.3 Port 1 Block Diagram (P15) ..................................................................................... 495
Figure B.4 Port 1 Block Diagram (P12) ..................................................................................... 495
Figure B.5 Port 1 Block Diagram (P11) ..................................................................................... 496
Figure B.6 Port 1 Block Diagram (P10) ..................................................................................... 497
Figure B.7 Port 2 Block Diagram (P24, P23) ............................................................................. 497