Datasheet

Rev. 3.00 Mar. 15, 2006 Page xxvi of xxxii
Figure 17.4 Sample SCI3 Initialization Flowchart ..................................................................... 319
Figure 17.5 Example of SCI3 Transmission in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit) ........................................................................... 320
Figure 17.6 Sample Serial Transmission Data Flowchart (Asynchronous Mode)...................... 321
Figure 17.7 Example of SCI3 Reception in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit) ........................................................................... 322
Figure 17.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (1) ..................... 324
Figure 17.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (2) ..................... 325
Figure 17.9 Data Format in Clocked Synchronous Communication .......................................... 326
Figure 17.10 Example of SCI3 Transmission in Clocked Synchronous Mode .......................... 327
Figure 17.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode) ................ 328
Figure 17.12 Example of SCI3 Reception in Clocked Synchronous Mode................................ 329
Figure 17.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)...................... 330
Figure 17.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
(Clocked Synchronous Mode)............................................................................... 331
Figure 17.15 Example of Inter-Processor Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A) .......................................... 333
Figure 17.16 Sample Multiprocessor Serial Transmission Flowchart ........................................ 334
Figure 17.17 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 335
Figure 17.17 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 336
Figure 17.18 Example of SCI3 Reception Using Multiprocessor Format
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).............................. 337
Figure 17.19 Receive Data Sampling Timing in Asynchronous Mode ...................................... 340
Section 18 I
2
C Bus Interface 2 (IIC2)
Figure 18.1 Block Diagram of I
2
C Bus Interface 2..................................................................... 342
Figure 18.2 External Circuit Connections of I/O Pins................................................................ 343
Figure 18.3 I
2
C Bus Formats ...................................................................................................... 357
Figure 18.4 I
2
C Bus Timing........................................................................................................ 357
Figure 18.5 Master Transmit Mode Operation Timing (1)......................................................... 359
Figure 18.6 Master Transmit Mode Operation Timing (2)......................................................... 359
Figure 18.7 Master Receive Mode Operation Timing (1) .......................................................... 361
Figure 18.8 Master Receive Mode Operation Timing (2) .......................................................... 362
Figure 18.9 Slave Transmit Mode Operation Timing (1) ........................................................... 363
Figure 18.10 Slave Transmit Mode Operation Timing (2) ......................................................... 364
Figure 18.11 Slave Receive Mode Operation Timing (1)........................................................... 365
Figure 18.12 Slave Receive Mode Operation Timing (2)........................................................... 365
Figure 18.13 Clocked Synchronous Serial Transfer Format....................................................... 366
Figure 18.14 Transmit Mode Operation Timing......................................................................... 367
Figure 18.15 Receive Mode Operation Timing .......................................................................... 368
Figure 18.16 Block Diagram of Noise Canceller........................................................................ 368