Datasheet

Rev. 3.00 Mar. 15, 2006 Page xxiii of xxxii
Figure 12.8 Clear Timing by TMRIV Input ............................................................................... 176
Figure 12.9 Pulse Output Example .............................................................................................176
Figure 12.10 Example of Pulse Output Synchronized to TRGV Input....................................... 177
Figure 12.11 Contention between TCNTV Write and Clear ...................................................... 178
Figure 12.12 Contention between TCORA Write and Compare Match ..................................... 179
Figure 12.13 Internal Clock Switching and TCNTV Operation................................................. 179
Section 13 Timer W
Figure 13.1 Block Diagram of Timer W..................................................................................... 183
Figure 13.2 Free-Running Counter Operation ............................................................................ 194
Figure 13.3 Periodic Counter Operation..................................................................................... 195
Figure 13.4 0 and 1 Output Example (TOA = 0, TOB = 1)........................................................ 195
Figure 13.5 Toggle Output Example (TOA = 0, TOB = 1) ........................................................ 196
Figure 13.6 Toggle Output Example (TOA = 0, TOB = 1) ........................................................ 196
Figure 13.7 Input Capture Operating Example ........................................................................... 197
Figure 13.8 Buffer Operation Example (Input Capture)............................................................. 198
Figure 13.9 PWM Mode Example (1) ........................................................................................ 199
Figure 13.10 PWM Mode Example (2) ...................................................................................... 200
Figure 13.11 Buffer Operation Example (Output Compare) ...................................................... 201
Figure 13.12 PWM Mode Example
(TOB = 0, TOC = 0, TOD = 0: Initial Output Values are Set to 0) ....................... 202
Figure 13.13 PWM Mode Example
(TOB = 1, TOC = 1,and TOD = 1: Initial Output Values are Set to 1) ................. 203
Figure 13.14 Count Timing for Internal Clock Source............................................................... 204
Figure 13.15 Count Timing for External Clock Source.............................................................. 204
Figure 13.16 Output Compare Output Timing ........................................................................... 205
Figure 13.17 Input Capture Input Signal Timing........................................................................ 206
Figure 13.18 Timing of Counter Clearing by Compare Match................................................... 206
Figure 13.19 Buffer Operation Timing (Compare Match)..........................................................207
Figure 13.20 Buffer Operation Timing (Input Capture) ............................................................. 207
Figure 13.21 Timing of IMFA to IMFD Flag Setting at Compare Match .................................. 208
Figure 13.22 Timing of IMFA to IMFD Flag Setting at Input Capture...................................... 209
Figure 13.23 Timing of Status Flag Clearing by CPU................................................................ 209
Figure 13.24 Contention between TCNT Write and Clear ......................................................... 210
Figure 13.25 Internal Clock Switching and TCNT Operation.................................................... 211
Figure 13.26 When Compare Match and Bit Manipulation Instruction to TCRW Occur at the
Same Timing .........................................................................................................212
Section 14 Timer Z
Figure 14.1 Timer Z Block Diagram .......................................................................................... 215
Figure 14.2 Timer Z (Channel 0) Block Diagram ...................................................................... 216