Datasheet

Section 7 ROM
Rev. 3.00 Mar. 15, 2006 Page 94 of 526
REJ09B0060-0300
7.2.4 Flash Memory Power Control Register (FLPWCR)
FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI
switches to subactive mode. There are two modes: mode in which operation of the power supply
circuit of flash memory is partly halted in power-down mode and flash memory can be read, and
mode in which even if a transition is made to subactive mode, operation of the power supply
circuit of flash memory is retained and flash memory can be read.
Bit Bit Name
Initial
Value R/W Description
7 PDWND 0 R/W Power-Down Disable
When this bit is 0 and a transition is made to subactive
mode, the flash memory enters the power-down mode.
When this bit is 1, the flash memory remains in the
normal mode even after a transition is made to
subactive mode.
6 to 0 — All 0 — Reserved
These bits are always read as 0.
7.2.5 Flash Memory Enable Register (FENR)
Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers,
FLMCR1, FLMCR2, EBR1, and FLPWCR.
Bit Bit Name
Initial
Value R/W Description
7 FLSHE 0 R/W Flash Memory Control Register Enable
Flash memory control registers can be accessed when
this bit is set to 1. Flash memory control registers
cannot be accessed when this bit is set to 0.
6 — 0 R/W Reserved
This bit can be read from or written to, but should not be
set to 1.
5 to 0 — All 0 — Reserved
These bits are always read as 0.