Datasheet

Section 4 Address Break
Rev. 3.00 Mar. 15, 2006 Page 67 of 526
REJ09B0060-0300
4.2 Operation
When the ABIE bit in ABRKSR is set to 1, if the ABIF bit in ABRKSR is set to 1 by the
combination of the address set in BAR, the data set in BDR, and the conditions set in ABRKCR,
the address break function generates an interrupt request to the CPU. When the interrupt request is
accepted, interrupt exception handling starts after the instruction being executed ends. The address
break interrupt is not masked because of the I bit in CCR of the CPU.
Figures 4.2 (1) to (2) show the operation examples of the address break interrupt setting.
NOP
instruc-
tion
prefetch
Register setting
• ABRKCR = H'80
• BAR = H'025A
Program
0258
025A
025C
0260
0262
:
*
NOP
NOP
MOV.W @H'025A,R0
NOP
NOP
:
0258
Address
bus
Interrupt
request
025A 025C 025E SP-2 SP-4
NOP
instruc-
tion
prefetch
MOV
instruc-
tion 1
prefetch
MOV
instruc-
tion 2
prefetch
Internal
processing
Stack save
Interrupt acceptance
Underline indicates the address
to be stacked.
When the address break is specified in instruction execution cycle
φ
Figure 4.2 Address Break Interrupt Operation Example (1)