Datasheet

Section 15 Watchdog Timer
(WDT1 is not available in the H8S/2695)
Page 708 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
15.2.2 Timer Control/Status Register (TCSR)
TCSR0
Bit : 7 6 5 4 3 2 1 0
OVF WT/IT TME — — CKS2 CKS1 CKS0
Initial value : 0 0 0 1 1 0 0 0
R/W : R/(W)
*
R/W R/W — — R/W R/W R/W
Note: * Only a 0 can be written, for flag clearing.
TCSR1
*
1
Bit : 7 6 5 4 3 2 1 0
OVF WT/IT TME PSS RST/NMI CKS2 CKS1 CKS0
Initial value : 0 0 0 0 0 0 0 0
R/W : R/(W)
*
2
R/W R/W R/W R/W R/W R/W R/W
Notes: 1. In the case of the H8S/2695, only 0 should be written to the TCSR1 register.
2. Only a 0 can be written, for flag clearing.
TCSR is an 8-bit readable/writable
*
register. Its functions include selecting the clock source to be
input to TCNT, and the timer mode.
TCSR0 (TCSR1) is initialized to H'18 (H'00) by a reset and in hardware standby mode. It is not
initialized in software standby mode.
Note: * TCSR is write-protected by a password to prevent accidental overwriting. For details see
section 15.2.5, Notes on Register Access.