Datasheet

Section 8 DMA Controller (DMAC)

(This function is not available in the H8S/2695)

Page 272 of 1434 R01UH0166EJ0600 Rev. 6.00

Mar 02, 2011

H8S/2633 Group, H8S/2633 F-ZTAT

H8S/2633R F-ZTAT

, H8S/2695

Bit 13—Source Address Increment/Decrement Enable (SAIDE): These bits specify whether

source address register MARA is to be incremented, decremented, or left unchanged, when data

transfer is performed.

Bit 14 Bit 13

SAID SAIDE Description

0 0 MARA is fixed (Initial value)

1 MARA is incremented after a data transfer

• When DTSZ = 0, MARA is incremented by 1 after a transfer

• When DTSZ = 1, MARA is incremented by 2 after a transfer

1 0 MARA is fixed

1 MARA is decremented after a data transfer

• When DTSZ = 0, MARA is decremented by 1 after a transfer

• When DTSZ = 1, MARA is decremented by 2 after a transfer

Bit 12—Block Direction (BLKDIR)

Bit 11—Block Enable (BLKE): These bits specify whether normal mode or block transfer mode is

to be used. If block transfer mode is specified, the BLKDIR bit specifies whether the source side

or the destination side is to be the block area.

Bit 12 Bit 11

BLKDIR BLKE Description

0 0 Transfer in normal mode (Initial value)

1 Transfer in block transfer mode, destination side is block area

1 0 Transfer in normal mode

1 Transfer in block transfer mode, source side is block area

For operation in normal mode and block transfer mode, see section 8.5, Operation.

Bits 10 to 7—Reserved: Can be read or written to.

Bit 6—Destination Address Increment/Decrement (DAID)