Datasheet

Section 7 Bus Controller
Page 230 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
7.6.2 DDS=0
When the DRAM space is accessed in DMAC single address mode, always perform full access
(normal access). The DACK output level changes to Low afer the T
r
state in the case of the
DRAM interface.
In other than DMAC signle address mode, burst access is possible when the DRAM space is
accessed.
Figure 7.31 shows the DACK output timing for the DRAM interface when DDS = 0.
T
p
φ
Read
Write
Note: n = 2 to 5
D15 to D0
D15 to D0
A23 to A0
T
r
T
c1
T
c2
row column
CSn (RAS)
CAS (UCAS)
LCAS (LCAS)
CAS (UCAS)
LCAS (LCAS)
DACK
HWR (WE)
HWR (WE)
RCTS = 1
RCTS = 0
Figure 7.31 DACK Output Timing when DDS=0 (Example Showing DRAM Access)