Datasheet

Section 7 Bus Controller
Page 224 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
• RAS up mode
To select RAS up mode, clear the RCDM bit of the MCR to 0. If DRAM access is interrupted
to access another area, the RAS signal level returns to High. Burst operation is only possible
when the DRAM space is contiguous. Figure 7.24 shows example timing in RAS up mode.
Note that the RAS signal level does not return to High in burst ROM space access.
External space
write access
T
p
A23 to A0
φ
T
r
T
c1
T
c2
T
c1
T
c2
DRAM
read access
DRAM
write access
T
1
T
2
D15 to D0
Note: n = 2 to 5
CSn (RAS)
CAS, LCAS
RD
HWR (WE)
Figure 7.24 Example Operation Timing in RAS Up Mode